Along the path from specification to silicon, the design of analog/mixed-signal chips comprises a variety of challenges. They are of technological, methodological, organizational, communicational, and business nature. Additionally, large gaps are to be managed among the individual challenges. Still up to now, approaches such as the “four eye principle” are used even in industrial practice in order to handle them. However, steadily increasing system complexity makes this an end-of-range model. Instead, EDA support gets more and more relevant in order to tackle both problem-specific and overarching design challenges. Based on the well-known V-model, the tutorial will discuss the current design approach and discusses systematic alternatives comprising EDA, tools, tool interfaces, and usability aspects. With this, the design challenges can be tackled in order to stick with the market needs and tight design schedules.
Quantum computing is an up and coming topic with a lot of attention not only from the scientific community but also increasing interest from industry. First, this talk introduces the topic from an electrical engineering point of view and explains why the possible use cases of a quantum computer make it so popular.
The underlying goal of the tutorial is to explain the two main types of circuits associated with a quantum computer, quantum circuits and specific (classical) circuits. For that the basic processing unit of a quantum computer, the so called qubit, is introduced first. With the qubits understood, quantum circuits can be addressed next. Here, the focus will be especially on understanding how such a circuit is similar or different to a classical circuit. Besides quantum circuits also a lot of classical electronics are necessary to realize a quantum computer. This talk will give an overview of the different kinds of classical electronics in a quantum computer and what circuit architectures are used in varying potential quantum computer implementations.
Todays integrated circuits (IC) incorporate more and more components to save area and increase reliability of the overall System on Chip (SoC). Yet the integration of analog, digital and RF systems on the same die suffers from various problems, one being the unwanted cross coupling, e.g. over power supply lines. Switching noise from digital circuits or high power ouput drivers propagate over the supply net to sensitive analog circuits and subsequently degrade their performance. Thus, these effects have to be taken into consideration early during the design and verification of mixed-signal ICs.
The simulation of an entire system such as an RF chip is not feasible on the transistor-level due to the very high computation effort that would be necessary. Event-driven simulation, widely used in digital circuit design, support the needed circuits sizes, but, even with the introduction of real number modeling, lack support for efficient description of analog or RF signal properties.
This presentation introduces a flexible framework, utilizing SystemVerilog user-defined data type (UDT) and net (UDN) in conjunction with the direct programming interface (DPI) to C++ to add the missing functionality. It is used to model a PLL testchip and investigate the influence of cross coupling through supply on the system performance.
The Printed Electronics (PE) devices and circuits are advantageous due to their ability to conform over different shapes and curvy surfaces which is needed for the advancement of numerous emerging applications including wearable systems, soft robotics, e-skin, bendable displays, and healthcare monitoring systems. This will also have an impact on the development of Internet of Things (IoT) concept where smart objects are required to be aware of and interactive with the unstructured environment. Additionally, PE systems are expected to revolutionise future electronics industry by providing cost-effective routes for processing diverse electronic materials at temperatures that are compatible with plastic substrates. Along with the flexible form factor, applications including IoT, smart healthcare etc. demands high device performance (fast data processing) leading to myriad machine-to-machine and/or human-to-machine connectivity at 5G communications. Accordingly, significant research efforts are on-going to manufacture electronic devices/systems with flexible form factor and high-performance. In this regard, printing of nanoscale inorganic structures have opened new avenues to achieve performances at par with silicon-based electronics.
In the first part of this tutorial, participants will gain an overview of various synthesis routes to obtain sub-100 nm inorganic semiconducting nanoscale materials (Nanowires (NWs), Nanoribbon (NRs) etc.) using bottom-up and top-down approaches. This includes wide variety of physical and chemical techniques such as metal assisted chemical etching (MACE), chemical vapour deposition (CVD) etc. The second part of this tutorial will bring together various printing techniques to integrate and assembly of grown nanoscale materials over flexible substrates. Potential capabilities and critical limitations of each printing technology will be highlighted, and possible solutions or alternatives will be discussed. The tutorial will also present some recent examples of high performance printed and flexible devices including transistors, sensors etc. using inorganic nanoscale materials.
In this tutorial, you’ll see the new integration of the Cadence® EMX® Planar 3D Solver into the Electromagnetic Solver Assistant of the Cadence Virtuoso® Layout Suite EXL and how to leverage it in the RFIC design flow, with a power amplifier (PA) design as example. You’ll learn how to perform fast and accurate EM analysis for selected passive components and nets in your design, while parasitic extraction for the rest of the design will be done in the Cadence Quantus™ Extraction Solution. Everything will be set up and driven from the Virtuoso Layout Suite EXL, keeping one golden schematic and one golden layout, without need of error-prone and time-consuming manual partitioning of the design into a block for parasitic extraction and a block for EM simulation. We will then demonstrate how to use the Cadence Spectre® X Simulator for post-layout simulation to predict accurate circuit performance.
The appearance of metastable states in flipflops by violations of setup- and hold times is a well known matter. In TDC circuits one cannot prevent metastabilities. In consequence, structural methods in practical designs, e.g. redundancies and multiple paths are required. Its real and practical function depends on the duration time of the metastabilities. There are some reasons that this durations are significantly less in SiGe- based ECL- and CML- structures in comparison to CMOS cells. In resume, we have characterized a lot of flipflop cells in the Common_ECL library to quantify the relevant duration of the metastable states. In result, the assigned VHDL models will show where is a metastability located in the structural design. After the defined duration, the model will switch to a random generated ‘1‘ or ‘0‘ value. This modelling concept can be a helpful tool to design fast TDC structures.
Neural networks are a pervasive technology, which is, however, still held back in the area of embedded systems by the high resource requirements, especially memory size, memory access time and power dissipation. In recent years, several different methods have been proposed to transform given neural networks in such a way that they can get by with much fewer resources while maintaining almost the same accuracy. This work reviews, categorizes and describes the state of the art in adapting and simplifying neural networks to make them better applicable to embedded systems. Even though we developed this study from a purely automotive context, the techniques described are also valid in other areas.