Signal Converters

11:00 – A 7-bit ECL-Based DTC with Improved INL

This paper presents a 7-bit digital-to-time converter (DTC) architecture based on emitter-coupled logic (ECL), designed for noise-critical and radiation-hardened applications where low-volume components are required and CMOS technologies may prove inadequate. The proposed DTC employs a variable-slope delay mechanism utilizing a digitally controlled capacitor array, achieving a resolution of 530 femtoseconds (fs) and a delay range of 67.3 picoseconds (ps). To enable the generation of clean square-wave outputs, two recovery stage topologies are analyzed. A modified ECL recovery stage, incorporating cross-coupled negative capacitance, is proposed to address the trade-off between phase noise and integral nonlinearity (INL). Simulation results indicate that the modified design achieves a systematic peak INL of 20 fs, representing a significant improvement over CMOS counterparts. The phase noise floor reaches −160.8 dBc/Hz, with a 400-Hz flicker noise corner frequency at a 200-MHz input signal, offering competitive noise performance. These benefits are realized at the cost of an increased power consumption of 24 mW.

11:20 – Noise Analysis of Constant-Slope Voltage-to-Time Converters

Voltage-to-time converters (VTCs) are critical components in time-domain (TD) analog-to-digital converters (ADCs). This paper addresses a gap in existing literature by analyzing noise in constant-slope (CS) VTCs. Noise contributions are examined across three operational phases: sampling, integration, and crossing-detection. Single-ended (SE) and common-mode (CM) integration approaches are compared, identifying the latter as effective in reducing noise. Moreover, it is shown that while the sampling and integration noise contributions are not affected by the VTC operating speed, faster VTCs suffer from a signal-to-noise ratio (SNR) degradation due to the crossing-detector (CD) noise contribution. Theoretical findings are validated through schematic-level simulations in a 22-nm FDSOI CMOS technology, observing agreement.

11:40 – Self-Calibration and Normalization of a 2D-Vernier TDC inside a Fractional-N ADPLL

This paper presents a calibration scheme to control the delay lines of a two-dimensional Time-to-Digital Converter (TDC) in the context of All-Digital Phase-Locked-Loops (ADPLLs). Special care is taken to make the TDC resolution track the momentous frequency of the oscillator of the ADPLL. The general scheme of the calibration as well as measurements are shown for samples fabricated in a 28 nm technology.

12:00 – Sub-100 ps LSB Time-to-Digital Converter with Voltage- or Current-Based Resolution Control

This paper describes the design of a sub-100 ps resolution Time-to-Digital Converter equipped with a time resolution control system. A controlled-voltage (CV) and a controlledcurrent (CC) approaches are proposed and compared. The key performance parameters, including timing resolution, dynamic power consumption, linearity, and jitter, are evaluated as a compromise with the system size. Simulations indicate that, in nominal conditions, the CV solution exhibits a power consumption of 2.2 mW and a resolution of 64 ps, while the CC method achieves a power consumption of 0.92 mW while maintaining a resolution of 80 ps.

12:20 – A 6-bit SAR ADC in TFT Flexible-Substrate

Flexible, low-cost wearable electronics call for fully flexible sensing systems, but integrating conventional silicon ADCs undermines cost and form-factor benefits. In this work, a successive approximation register (SAR) ADC in thin-film transistor (TFT) is proposed and entirely implemented on a flexible substrate. The SAR-ADC, operating at 20 kHz and powered at 3 V, features a fully differential architecture with a 6-bit capacitive DAC and a single comparator to enhance robustness against charge injection from switches and to minimize area. Circuit-level simulations demonstrate excellent linearity (INL/DNL within ±0.5 LSB) alongside low power consumption (0.67 mW), outperforming prior flexible implementations in resolution (ENOB = 5.83 bits) and energy efficiency. The ADC's architecture, design optimizations, and detailed simulation results are presented, confirming its viability as a key enabler for next-generation flexible body-sensing electronics.

12:40 – Design of a Current-to-Frequency Converter with 0.18 pJ and 334 Hz/nA in 180 nm BCD-SOI

This paper presents a process, voltage, and temperature (PVT) insensitive current-to-frequency converter (CFC)targeting radiation sensing applications to withstand a total ionizing dose (TID) of 450 krad. The proposed architecture features an analog switching matrix, a Schmitt trigger-based debouncing circuit, and cascaded buffers within a feedback controlled mechanism. The design is implemented in 180 nm BCD-SOI technology, with a high-voltage and a high-resistive substrate have been used to realize the particle-sensing diode, occupying a chip- area of 0.0131 mm2. The post-layout simulation results of proposed architecture confirm a linear sensitivity of 334 Hz/nA and an input-referred noise current of 1.26 µArms over a frequency band of 66.98 MHz. The suggested CFC achieves an energy-efficient figure-of-merit (FoM) of 0.18 pJ, with an output frequency range of 19 kHz to 67 MHz, for input currents spanning from 58 nA to 200 µA. The circuit maintains stable operation across a wide temperature range from –40 °C to 125 °C and demonstrates higher performance compared to state-of-theart solutions.