Power Circuits II

16:00 – A Comparative Analysis of NMOS Linear Dropout Voltage regulators in 65nm CMOS technology

This paper proposes a comparison of different topologies of NMOS low dropout voltage regulators (NMOS-LDOs) designed for low-voltage and low-power applications. Different topologies are considered, namely the conventional one, in which the error amplifier drives directly the pass transistor, the charge pump-assisted LDO, in which the error amplifier is supplied by a charge pump, and a new solution, in which the charge pump acts as a signal amplifier and directly drives the pass transistor. A comparative analysis is carried out on a theoretical basis and through simulation results on CMOS 65-nm implementation.

16:20 – A High-Speed Comparator For SiC Power MOSFET Short Circuit Detection

Recent years have seen the increasing adoption of wide bandgap semiconductors, such as GaN power switches and SiC MOSFETs. Compared to silicon power devices, these technologies offer significant advantages, including lower Rds(on), reduced losses, and enhanced high-temperature tolerance. One of the main drawbacks of those devices is the short circuit withstand time, and so new short circuit protection strategy must be developed. This paper presents a novel Integrated Circuit (IC) designed for short-circuit detection in Silicon Carbide (SiC) MOSFETs, leveraging an integrated shunt resistor for efficient current sensing. The proposed solution enables fast detection of short circuits, achieving response times of approximately 50 ns without introducing detrimental parasitic inductance. The topology of integrated comparator is a self-referred ΔVbe, it is capable of detecting voltage drop of about 36 mV across the shunt resistor and it compensates the Rshunt shift over temperature to ensure fast reliable operation. Simulation results demonstrate the effectiveness of the current sensing method, with a minimal variation in current threshold over temperature, ensuring robust performance in various applications, including electric vehicles and renewable energy systems.

16:40 – Detailed Modeling of a PFM Buck-Boost Converter suitable for Low Power Applications

This work proposes a method for modeling an hysteretic DC-DC Buck-Boost regulator with Pulse Frequency Modulated (PFM) control. The performance of some DC-DC converters such as single-inductor multiple-output (SIMO) converters strongly depends on inductor current ripples, making the conventional modeling methods not usable for fully predict the complete behavior of the system. This paper proposes a detailed analysis of all the blocks constituting a generic regulation system, reporting analytical expressions in both frequency and time domain, and relating it to the behavior of the system.

17:00 – Interconnected Switched-Capacitor Based DC-DC Converters to Enhance Input-to-Output Conversion Range and Driving Capability

In this paper, we propose an Interconnected switched-capacitor(SC) based DC-DC converter topology named as Staggered-Stacked converter. In this proposed topology, we can use multiple converter modules having a fixed conversion ratio and a given voltage overstress limit to get an overall converter with a higher voltage overstress limit, resulting enhanced input-to-output conversion range. Moreover, it provides multiple conversion ratios along with enhanced driving capability. The configuration has been analyzed and a prototype design has been developed utilizing multiple constituent converters having a 2:1 conversion ratio and an overstressed voltage limit of 2.75V. The prototype Staggered-Stacked converter has two output ports with 3:2 and 3:1 ideal conversion ratios and, an input supply voltage limit of 4.1V. The prototype converter has been simulated in a standard 65nm CMOS process with an input voltage of 3.5V. It produces two output voltages of 2.1V @Port 1 and 0.96V @Port 2 with a driving capability of 346mA maximum load current at Port 1 while maintaining a good efficiency of 81.43%.

17:20 – A Time-Based Integrated Three-Level Buck Converter with Enhanced Flying Capacitor Balancing Feedback Loop

Flying capacitor multi-level (FCML) converters offer high efficiency but pose challenges with flying capacitor balancing, particularly under light load conditions. Improper balancing increases switch voltage stress, negatively affecting performance and device longevity. In this paper, a time-based dual-loop control method is introduced for a 10-MHz three-level buck converter (TLBC), integrating flying capacitor and output voltage regulation into a unique structure. Compared with previous work, the dual-loop control directly addresses the light load balancing issues already mentioned, ensuring adaptive regulation across the full load range. Simulation in SIMetrix/SIMPLIS environment results and theoretical analysis demonstrate the effectiveness of this technique, enhancing the performance of time-based control in dynamic response in portable systems. The controller was designed in a 180-nm BCD technology.

17:40 – Design of a Sub-uA Bias Current, Multi-Stage Comparator with Delayed Positive Feedback for Dynamic Gain Enhancement

In many battery-powered applications, reducing the quiescent current consumption of switching converters is an essential feature that helps extend the battery life time of the device. In this frame, DC/DC converters with variable frequency controls are preferred to reduce switching activity and associated losses. To further enhance efficiency, most of the blocks inside the controller are set to idle mode, except for very few components, such as the output comparator. In this paper, the design of a comparator with sub uA bias current is presented. The proper number of preamplifier stages is derived by evaluating gain, delay, and offset. To further enhance the transition speed, a delayed weak-positive feedback comparator is proposed. The proposed structure exploits the delay to operate as a strong-arm latch during transients while maintaining the stability in normal operation. Finally, the comparator is designed using BCD (Bypolar DMOS CMOS) technology, and its static and dynamic performances is verified with transistor-level simulations.