Power Circuits I

11:00 – A 49.7 nA Energy Harvester with Simultaneous Multi-Source Harvesting and Multi-Load Regulation Achieving 83.8% Peak Efficiency

This article presents a single-inductor multi-source energy harvester capable of simultaneously collecting energy from up to two DC sources and one AC source while regulating three loads with the support of a super capacitor. The proposed architecture incorporates a hybrid buck-boost/boost circuit as well as a double pile-up circuit for AC and DC energy harvesting respectively. It facilitates multi-source maximum power point tracking (MPPT) and multi-load regulation within a single cycle, efficiently storing and reusing surplus ambient energy with the assistance of the super capacitor. The harvester dynamically adapts to its operating environment, automatically switching between various working modes based on the available energy sources and the demand of the output loads. Implemented in 180 nm BCD process, the prototype occupies a total area of 2.5 mm². Simulation results demonstrate successful transitions from self-start-up (SSU) mode to multi-source energy harvesting and multi-load regulation (MSEH-MLR) mode, achieving a 49.7 nA quiescent current with a peak efficiency of 83.8%. The PZT energy extraction improvement (FoM) is 719%, increasing by 159% compared to the state-of-the-art works.

11:20 – Regulator-less Stacked Power Delivery with Photovoltaic Energy Harvesting

This paper presents a regulator-less stacked-power delivery using solar cells as the photovoltaic (PV) energy harvester. There are critical challenges for current delivery in integrated circuits on chips while operating at low voltages. To address this issue, voltage stacking is a suggested method to deliver power in “a series” instead of the traditional "parallel" approach. This paper utilizes voltage stacking as the power delivery approach and an energy harvester with maximum power point tracking (MPPT) as the supply source. The harvester uses a nanofarad bulk capacitor (Cbulk) as a small storage element. The proposed method proves advantages compared to the traditional. It requires half the number of solar cells (i.e 3) while the traditional one requires 6 solar cells. The area of PV harvester in traditional and proposed is approximately 32,897mm² and 16449mm² respectively. This results in a 50% smaller area along with a decrease in cost. The architecture also results in Cbulk size reduction from 2.7 nF in traditional to 1 nF in the proposed, resulting in improved area efficiency and faster charging to the target supply voltage. Moreover, the architecture reduces the current by almost 50% which mitigates the challenge of low current delivery and can lead to supply noise reduction and better power delivery efficiency.

11:40 – Design of an Ultra-Low Power Start-up Circuit for Micro-Power Management Units in Energy Harvesting Applications

In the last decades, the Internet of Things paradigm has been bringing the vision of ubiquitous smart sensor networks closer to reality. However, the battery-powered devices suffer from recharging and environmental issues. In this context, energy harvesting, particularly from RF sources, is an effective solution to power smart sensors on-demand. In this paper, an integrated Start-Up (SU) circuit for a RF-powered micro-power management unit (MPMU) is presented. In power-constrained applications, the SU circuit needs to self-start from the low voltages and powers, and with the high output source resistances typical of rectennas, accumulating enough energy to kickstart the main converter. The circuit is designed in a STMicroelectronics 110-nm technology, and simulations show operation from 0.5 µW and 125 mV in the typical corner, reaching an output voltage of 1.2 V.

12:00 – High-Efficiency Adaptive Off-Time Control for 6.78MHz CMOS Active Rectifier Compliant With AirFuel WPT Standard

This paper presents an adaptive algorithm designed to optimize the turn-off timing of a CMOS active rectifier compliant with the resonant AirFuel standard at 6.78 MHz. The proposed algorithm was applied to the case of a wireless power transfer (WPT) system for consumer applications implemented in a 90-nm BCD process. By employing delay lines and an asynchronous finite state machines (AFSM), the proposed solution achieves optimal turn-off timing for the RX full-bridge rectifier, minimizing reverse current and improving power conversion efficiency (PCE). Cadence Virtuoso simulations—under conditions of an input voltage of 12 V, an output voltage of 20 V, coupling coefficients ranging from 0.15 to 0.4, a load current varying from 137 mA up to 300 mA and a delivered power range of 0–5 W- demonstrate a significant PCE improvement, increasing from 20–43% to 80–87% with the proposed approach. The proposed rectifier, thanks to the employed algorithm optimizing the turn off timing maintains a near-constant 96% efficiency across a wide range of operating conditions.

12:20 – Efficiency Comparison of FVF-Based LDO Voltage Regulators for Ultra-Fast Response Time

This paper compares, as a function of the efficiency, the small-signal performances of two output stage topologies for the development of ultra-fast response time Low-Dropout regulators (LDOs), based on the Flipped-Voltage Follower (FVF) cell. Although one of the alternatives achieves improved efficiency for a given bandwidth, it suffers from reduced phase margin. To solve this issue, a technique able to extend the output stage bandwidth with improved efficiency and phase margin is presented. The implementation of a schematic-level prototype LDO in a 28-nm bulk CMOS technology, which exceeds state-of-the-art dynamic performances, confirms the effectiveness of the proposed solution.

12:40 – Comparative Study of High-Voltage High-Conversion-Ratio Step-Down DC-DC Converters for Light Load Applications

The evolution of power architectures in domains such as IoT, smart homes, and electric vehicles has driven the adoption of higher supply voltages to improve energy efficiency and minimize distribution losses. Consequently, there is a growing demand for wide-input-range DC-DC converters that can deliver stable and efficient regulation, particularly under light-load conditions in decentralized systems. In this context, accurately evaluating and quantifying power losses has become a critical design consideration. This work presents a comprehensive analytical methodology for estimating power losses and efficiency in the power stage of two step-down DC-DC converter topologies: a half-bridge converter and a resonant converter. The analysis is supported by explicit equations, providing insight into the dominant loss mechanisms. The proposed model is validated through circuit-level simulations, demonstrating good agreement with theoretical predictions.