Neural Networks and ML

11:00 – Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS

We report on the design of a receiver for high- speed I/O in 22nm CMOS compliant with the PCIe 6.0 standard at 64 Gb/s with PAM-4 coding. A quarter-rate ar- chitecture is considered, implementing equalization strategies such as Continuous-Time Linear Equalization (CTLE) and Decision-Feedback Equalization (DFE, direct). The latter is fully adaptive thanks to the use of error samples. The Clock- and Data-Recovery (CDR) circuit controls an array of phase interpolators working at 8 GHz. For most of the building blocks, we report post-layout simulation results. Simulations including selected circuit blocks, behavioral models and the RTL are used to assess the performance of the whole receiver including the CDR and the fully-adaptive algorithms.

11:20 – When Simpler Models Win: The Limits of Parameter Sharing Neural Networks in Cross Technology SRAM Analysis

Static Random Access Memory (SRAM) is a critical component in modern electronics, and accurate predictions of its stability are essential for optimizing performance across various technology nodes. In this paper, we propose a neural network (NN) model with parameter sharing designed specifically for cross-node SRAM stability prediction, enabling knowledge transfer between different technology nodes. To ensure the reliability of our model, we use a high-sigma verifier (HSV) to simulate actual statistical values, providing a thorough evaluation of the model performance under varying conditions. While the NN model demonstrates promising results, we find that the machine learning (ML) approach outperforms the NN model in predicting key SRAM metrics, including Access Disturb Margin (ADM), Write Margin (WRM), and Ireadmin. We provide a detailed comparison between both approaches, highlighting the strengths of the ML model in achieving more accurate predictions, while also demonstrating the potential of the NN model for future improvements in SRAM stability prediction. Such prediction aims to transform design decision making and substantially improves early-stage stability evaluations.

11:40 – Runtime Reconfigurable FPGA Accelerator for Tactile Texture Classification Based Shallow CNN

Electronic skin (e-skin) represents a transformative advancement in human-machine interaction, offering tactile sensing capabilities that emulate the mechanical and physiological properties of human skin. The integration of edge AI for this type of application enables sensors to process complex data in real time, but deploying AI models on resource-constrained embedded platforms remains a challenge due to limitations in memory, energy efficiency, and computational power. In this work, we present the case study of a 1D-CNN adaptive accelerator for texture recognition implemented on an FPGA, leveraging a design flow that offers support for the design and deployment of quantized CNN accelerators with runtime reconfiguration capabilities. As a step toward a future project that combines an FPGA with a tactile acquisition interface, we extended the design flow to support 1D-CNNs and subsequently analyzed the effects of quantization on the CNN accelerator's precision, resource usage, and power consumption.

12:00 – A Neural Network-Based Controller for DC-DC Buck Converter for Improved Resilience

This paper presents a novel Neural Network (NN) based control strategy for DC-DC Buck converters aiming to enhance the dynamic system response in face of external disturbances. The proposed controller employs a compact multilayer perceptron, and it is trained online through supervised learning strategy. Its ground-truth labels correspond to the optimal control actions that minimize the converter output voltage error. This results in a tiny NN, paving the way for embedded hardware implementations. The validation of the proposed NN-based controller is conducted via circuital simulations, demonstrating significant improvements in transient response compared to conventional control techniques.

12:20 – A 1.2-fJ/MAC, 7-fJ/ReLU, 5.9-b ENOB, All-Analog Neural Network Computing Macro

Artificial intelligence at the edge requires ultra energy efficient computing circuits. Computing in the analog domain can offer orders of magnitude higher energy efficiency compared to the digital domain. We present and characterize an all-analog neural layer macro to compute fully-connected neural networks without the involvement of data converters and digital signal processing in the data path. Our charge domain multiply-accumulate (MAC) units operate with 1.2 fJ/MAC in average and the ReLU-voltage-to-time converter with 7 fJ/ReLU. The effective resolution is 5.6 b for the weights, 4.9 b for the activations and 5.9 b for the dot product. An accurate TensorFlow model is developed for hardware-aware training.

12:40 – Machine Learning Models for EMG-Based Diagnosis of Neuromuscular Disorders

Neuromuscular disorders (NMDs), such as myopathies and neuropathies, affect the communication between nerves and muscles and often lead to serious functional impairments. This study investigates the impact of preprocessing methods and machine learning models on the automated classification of NMDs using electromyography (EMG) data. We compare Convolutional Neural Networks, Extreme Gradient Boosting, and Light Gradient Boosting Machine on two binary classification tasks: Healthy vs. Myopathy and Healthy vs. Neuropathy. The analysis is conducted on an open dataset of invasive needle EMG recordings, serving as a preliminary step toward the future use of non-invasive surface EMG in wearable diagnostic tools. The results highlight the importance of preprocessing and show promising performance across all models.