Filters and Oscillators

11:00 – Analysis of a gm-C Complex Filter for Low Power Wireless Receivers

A simple topology for a gm − C complex filter to be used in a low-IF low power wireless receiver is proposed and analyzed. The result is a set of close-form equations that allows for a straightforward design procedure. The proposed analysis is validated by transistor-level simulations on a design example in a 22 nm CMOS technology.

11:20 – High-Level Design of AC-Coupled Gm-C Biquads for Power-Line Communication

This paper presents a high-level design methodology for AC-coupled Gm-C biquad filters tailored for power-line communication (PLC) systems, specifically addressing the stringent requirements of battery monitoring applications (BMA). We analyze two standard biquad topologies, the Passive-Feedback Biquad (PFB) and the Active-Feedback Biquad (AFB), deriving key design equations and evaluating their performance characteristics relevant to BMA. Focusing on system-level perspective, we explore trade-offs between digital tunability and modularity for optimizing design effort in multichannel systems where different battery modules are coupled to a shared power network. In addition, we discuss the impact of parasitic capacitance, the finite output resistance of the filter transconductors, and the input impedance characteristics of both topologies, leading to clear design indications. Our findings offer valuable insight for designing efficient and adaptable analog front-end circuits for PLC networks.

11:40 – Ultra-Low Phase Noise BAW-Based Cross-Coupled Oscillator in 28 nm CMOS Technology

This paper presents a comprehensive analysis of a CMOS cross-coupled oscillator in 28 nm CMOS technology using a BAW resonator to achieve an ultra-low phase noise performance with low power consumption. The design methodology relies on the gm/ID resourceful approach, promoting direct relation with noise. The efficiency and phase noise optimizations are carried out along with parasitic oscillation suppression to enhance the overall stability and performance of the circuit. The corner simulation shows an oscillation at 2.42 GHz, with a power consumption of 1.16 mW, and achieving a phase noise of -157.6 dBc/Hz at 1 MHz offset.

12:00 – A SiGe Oscillator with Second Harmonic Control Technique for mmWave Applications

This paper presents a novel Colpitts-based oscillator employing SiGe:C 130 nm bipolar devices provided by IHP foundry, featuring a transit frequency of 350 GHz and a maximum oscillation frequency of 450 GHz. Designed for mmWave and sub-terahertz applications, the oscillator operates at a fundamental frequency of 220 GHz, delivering an output power of 4 dBm. Simultaneously, it generates a second harmonic signal at 440 GHz with an output power of -4.2 dBm, enabled by an innovative second harmonic regulation technique that enhances harmonic extraction and efficiency. A dedicated Second Harmonic Optimizer (2H-OPT) is integrated into the design to efficiently capture and amplify the second harmonic generated by device nonlinearity. Simulation results confirm that the oscillator maintains reliable performance, with high output power, a phase noise of -89 dBc/Hz at a 10 MHz offset, and stable frequency operation. These attributes make the proposed design an attractive candidate for high-frequency applications in communications, sensing, and imaging.

12:20 – A Highly-Linear, Power-Supply-Isolated Current-Controlled Oscillator for Data Conversion

Single-ended open-loop oscillator-based analog-to-digital converters benefit significantly from CMOS technology scaling due to their digital-intensive hardware. However, a drawback of these architectures is the poor linearity of the ring oscillators, particularly the high even-order harmonic distortions. In this work, we propose a strategy to minimize even-order harmonic distortions in a resistive-network-linearized ring oscillator by optimally biasing in the global maxima of the gain of the oscillator. The proposed current-controlled oscillator (CCO) is implemented in a 130 nm CMOS technology, occupying an area of 714 µm2 and consuming 48 µW of power. Evaluated using SPICE simulations with layout-extracted parasitics and process variations, the proposed CCO achieves in nominal an input range of 13.5 µApp (6.5 µA more than previously reported implementations), THD of -69 dBc (10 dBc better than the state of the art), and a HD2 of -79 dBc. The SNDR FoM is improved by a factor of 16 under nominal conditions and by a factor of 5.4 in the worst-case process corner, demonstrating that the CCO maintains state-of-the-art performance across process variations.

12:40 – High-Frequency Oscillator with Spread Spectrum and Automatic Amplitude Control Loop

This paper presents the design of a 750 MHz oscillator in 0.4 µm CMOS technology, equipped with a spread spectrum circuit for EMI reduction and an automatic gain control loop for the stabilization of the output signal’s amplitude, which, according to the specification, must not drop below 0.9 V in any case. The spread spectrum circuit, based on a capacitive tank and a pseudorandom bits generator clocked at 15 MHz, is sized to produce a 30 MHz spread over the central frequency. The automatic gain control loop reduces variations in the output signal amplitude in response to variations in signal frequency, which also results in a reduction both in emissions and in current consumption. In nominal conditions at central frequency the differential signal amplitude is 1.40 V, the current consumption is 2.31 mA and the maximum variation of amplitude caused by the spread spectrum is limited to 2.9% of the central value. In the worst-case scenario over PVT and frequency variations, the amplitude is reduced to 1.01 V, still with a margin on the specification.