Digital Circuits and Systems II

16:00 – DTMOS Schmitt-Trigger Standard Cells based Frequency Divider Operating at 60mV

Dynamic Threshold voltage MOS (DTMOS) Schmitt-Trigger standard cells are proposed to improve the Ion/Ioff ratio and enhance robustness against process variations and mismatch. A D flip-flop and frequency divider employing DTMOS Schmitt-Trigger standard cells are implemented in a commercial 130 nm SOI CMOS process. Based on post-layout Monte Carlo simulations, the yield of the D flip-flop and frequency divider is 99.7% and 99.4%, respectively, at a supply voltage of 60 mV. The minimum energy point of the frequency divider lies at 160 mV and energy per transition is 39.2 fJ. Both the D flip-flop and the frequency divider can operate at a supply voltage as low as 50 mV.

16:20 – A Triple Latched Ultra-Low-Voltage Rail-to-Rail ICMR Standard-Cell Based Comparator

A triple latched NOR2-based standard-cell comparator, with Rail-to-Rail input common mode range (ICMR) is presented. The topology aims at lowering the clock-to-output delay with respect to the previously presented standard-cell-based comparators with Rail-to-Rail ICMR feature. Moreover, the achieved speed is higher than the NOR2-based topology previously presented by the authors, and the improvements are in the order of 3× to 20× higher speed and 3× to 12× lower PDP, with respect to the other standard-cell-based Rail-to-Rail ICMR topologies in literature. The circuit has been validated considering a 45nm CMOS technology and the power supply voltage scaled down to 0.6V, 0.3V and 0.15V.

16:40 – RelaxCIM: A low-power ADC-less relaxation oscillator readout cell for CIM accelerators with up to 11-bit resolution and minimal area overhead

Compute-in-memory (CIM) architectures aim to become a standard for accelerating AI algorithms. Yet, the performance of analog CIM implementation is generally limited by the resolution of their readout cell, typically composed of a transimpedance amplifier and an ADC. To tackle this issue, this paper presents RelaxCIM, a novel approach to solving quantization issues in analog current-based CIM accelerators. By replacing traditional resource-intensive ADCs with a combination of relaxation oscillators and digital counters, we maintain the full precision required for vector-matrix multiplication operations with up to 11-bit resolution, while limiting the area and power consumption to resp. 0.0012 mm sq. and 0.3 mW. Our proposed method is particularly advantageous in scenarios where neural network inputs exceed the hardware VMM capacity, mitigating quantization errors and finite precision limitations.

17:00 – 20 MeV⋅cm²/mg Linear Energy Transfer Radiation Tolerant Six-Transistor Static-Random-Access-Memory Cell in 28 nm CMOS Technology

This paper presents the complete design and electrical simulations of a volatile memory cell in 28 nm CMOS bulk technology resistant to Single Event Upset at 20 MeV∙cm²/mg of Linear Energy Transfer. The circuit topology of the cell is based on a classic six-transistor structure, in which the storage latches have a feedback impedance which allows to reduce the current contribution on the pull-down/pull-up network in case of upset events, avoiding unwanted setup of the stored bit. To demonstrate the robustness of the cell against upset events, the current pulse signal generated by the incident particles passing through the silicon substrate was modelled and generated by MATLAB equations and subsequently moved to SPICE environment simulator for performance verification. In the presence of an incident charge pulse of 15.5 fC (whose duration is of the order of 400 ps) the single event current pulse has a peak of 60 μA and generates a voltage variation of -250 mV with respect to the ‘1’ logic value (0.9 V as nominal supply voltage for Standard Process MOS Transistors in 28 nm CMOS) with a recovery time below 1% of 0.9 V of only 600 ps. The simulations were carried out assuming to operate in a SRAM bank of 32 words of 32 bits, thus including the capacitive effects of the bit-line routing. The cell operates with 10 ns per operation (for the READ, WRITE and HOLD states, respectively) and has an energy/bit of 108 fJ, 64 fJ and 126 fJ, for the WRITE, HOLD and READ operations, respectively.

17:20 – Digital OTA with Floating-Inverter Input Stage and Isolation Resistor-Based Frequency Compensation for Ultra-Low Power CT-ΣΔ Modulators

This paper presents a fully differential floating-inverter-input digital operational-transconductance-amplifier (FI-DIGOTA) featuring isolation resistor-based frequency compensation. The proposed FI-DIGOTA achieves a DC gain of 59.2 dB, a gain-bandwidth product (GBP) of 50 kHz, and a phase margin (PM) of 47.5° while operating at an ultra-low (UL) supply voltage of 0.4 V. The power consumption of the proposed FI-DIGOTA is 7 nW, making it well-suited for energy-constrained applications. A first-order continuous-time ∆Σ (CT-∆Σ) modulator utilizing an integrator based on the proposed FI -DIGOTA is proposed as an application example and achieves a signal-to-noise-and-distortion ratio (SNDR) of 44 dB, a spurious-free dynamic range (SFDR) of 55.18 dB, and an effective number of bits (ENOB) of 7.016 bit over a 500 Hz bandwidth at 100 oversampling ratio (OSR).

17:40 – Design of hardware-efficient radix-22 FFT processors with approximate fixed-width multipliers

In this paper, we propose the design of a low-power radix-22 SDF FFT processor exploiting optimized multiplications. In our implementation, multiplications are skipped when FFT coefficients equal zero and one to reduce the switching activity in multipliers. A fixed-width approach is also adopted to further decrease hardware burden when coefficients are non-trivial, and a probabilistic study of remaining partial products is proposed to neglect terms that are often zero. Truncation at the multiplier output is also devised for further circuital simplification. Analyses of accuracy, expressed in terms of SNR and MSE, reveal the possibility to achieve satisfactory results having also high area and power reductions (up to 29.5% and 31%, respectively). The proposed FFT suits also well for an OFDM receiver, showing favorable performance under several noise levels in an AWGN channel.