Digital Circuits and Systems I

11:00 – Efficient FPGA Readout Architecture for MKIDs: A DSP-Light Approach

The Digital Down Converter (DDC) is a key component in many signal processing systems. In our FPGA-based readout electronics for the CONCERTO instrument—a mm-wave imaging system employing an array of 400 Microwave Kinetic Inductance Detectors (MKIDs)—DDCs are used to process a frequency-multiplexed signal. However, each MKID requires a dedicated DDC consisting of two multipliers, resulting in a total of 800 multipliers. This substantially contributes to the overall utilization of our FPGA’s Digital Signal Processing (DSP) resources, reaching 70.76%. Such high resource usage poses a scalability challenge for the next-generation instrument, where the number of MKIDs is expected to double to meet higher resolution requirements. To address this, we propose a squared-signal demodulation technique that maintains the same spectral readout performance of the current DDC implementation while significantly reducing resource usage. The proposed method reduces DSP utilization by 28.98%pt, enabling support for larger MKID arrays without compromising signal fidelity.

11:20 – Real-Time Histogramming Module for a Multichannel ADC Board

Multichannel data management poses considerable challenges; it is essential in a world increasingly driven by big data in both scientific research and industrial applications. Histogramming remains a key operation for analyzing signal distributions, noise profiles, and threshold behaviors in multichannel detector systems. This paper presents a fully hardware-embedded real-time histogramming module integrated into a multi-purpose digitalizer (MPD) platform based on an Xilinx Kintex-7 FPGA. The system captures 12-bit ADC data at 40 MHz across multiple channels and allows direct user access via a 1 Gbps TCP/IP Ethernet interface. Moreover, a dual-port block RAM architecture supports concurrent read and write operations across separate acquisition and system clock domains. At the same time, a compact control finite state machine ensures seamless state transitions without introducing dead time. Unlike hybrid FPGA-CPU architectures, the proposed design is entirely spatial and self-contained, making it well-suited for high-throughput, low-latency data.

11:40 – A Signal Quality Assessment Algorithm for Photoplethysmographic Sensors

The growing demand for reliable wearable devices that can continuously monitor vital signs and track health under various conditions, impose challenging constraints on battery life. Wearable devices typically include a photoplethysmogram (PPG) sensor, which is used for various applications such as monitoring heart rate (HR) and blood oxygenation (SpO2). The efficiency of these applications depends on the quality of the PPG sensor, which acquires raw data through the analog front-end and transmits it externally. This paper presents a novel Register Transfer Level (RTL) block that evaluates the quality of the PPG signal. This Signal Quality Assessment (SQA) RTL block is derived from postprocessing algorithms and converted into a real-time singlesample evaluation algorithm and provides significant benefits to the sensor with minimal overhead in terms of energy and area consumption.

12:00 – A low power logic control core with SPI interface for switches arrays applications

This paper proposes an enhanced low power logic control block equipped with SPI interface intended for controlling arrays of switches. Validation of the proposed control block architecture was achieved through silicon measurements at chip level which contains the digital block with a matrix structure meant to be addressed and updated by the controller. This design was realized in 65 nm CMOS technology, targeting operating voltages ranging from 1.0 V up to 2.5 V, across a wide interval, -40°C - 125°C. High speed operation could be achieved, having a frequency operation above 70 MHz, very fast propagation delays, and below 2 ns data setup values.

12:20 – Energy-Efficient Approximate Bus Encoder for I2C in an Industrial Photoplethysmography Smart Sensor

In ultra-low-power wearable sensors, serial buses such as I2C significantly impact the total energy budget. Approximate bus encoding has emerged as a key strategy for energy-efficient data transmission. While ACME, a state-of-the-art encoding method, has proven effective, it lacks I2C compatibility. This work presents the first fully integrated ACME encoder into the I2C interface of a novel PPG sensor prototype, redesigning it for compatibility and filling the gap from an industrial perspective by providing accurate power evaluations that reflect realistic application scenarios. The results demonstrate that transmission energy and system energy savings reach 33.4% and 8.16%, respectively, with negligible error and overhead.

12:40 – Benefits of FPGAs for Deep Learning Acceleration in Spacecraft Systems

Artificial Intelligence (AI)-driven autonomous onboard data processing is essential for future space missions, enabling timely decision-making in scenarios like planetary exploration, in-orbit servicing, and Earth Observation (EO). To overcome latency and reliance on ground control, AI models must run directly onboard. While edge AI and low-power accelerators have improved deep learning (DL) deployment on embedded systems, most commercial hardware lacks the radiation tolerance needed for deep-space missions. Space-qualified Field Programmable Gate Arrays (FPGAs) offer a robust solution, combining energy efficiency, fault tolerance, and in-flight reconfigurability. This adaptability allows spacecraft to update AI models during missions without hardware changes. This paper reviews DL acceleration strategies for space applications, focusing on image processing, and presents a case study using the ANHEO platform, developed by TSD-Space and co-funded by the Italian Space Agency (ASI), demonstrating the benefits of FPGA reconfiguration in spaceborne AI systems.