Biomedical Circuits and Systems I

16:00 – iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator

Implantable devices enabling intracranial electroencephalography (iEEG) seizure detection, allow epilepsy patients to receive potentially life-saving alerts before seizures occur. But this requires an always-on, accurate, real-time, and energy-efficient onset classification algorithm and hardware implementation. To meet tight energy budgets and extend battery life, previous works employ dense HDC over traditional neural-network-based methods. However, dense HDC still requires considerable switching energy due to the dense hypervectors. Sparse HDC, on the other hand, has the potential of further reducing the energy consumption, yet at the expense of having to support more complex operations and introducing an extra hyperparameter, the maximum hypervector density. To improve the energy and area efficiency of the sparse HDC operations, this work introduces the compressed item memory (CompIM) and simplifies the spatial bundling. We also analyze how a proper hyperparameter choice improves the detection delay compared to dense HDC. Ultimately, our optimizations achieve a 1.73x more energy- and 2.20x more area-efficient hardware design than the naive sparse implementation. We are also 7.50x more energy- and 3.24x more area-efficient than the dense HDC implementation. This work highlights the hardware advantages of sparse HDC, demonstrating its potential to enable smaller, safer brain implants with a substantially extended battery life compared to the current state-of-the-art.

16:20 – A Two-Step Charge Balancing Circuit with Sub-mV Accuracy for High-Voltage Neurostimulators

The residual charge accumulated across the electrode tissue interface during electrical neurostimulation causes severe tissue damage and electrode corrosion. By minimizing this charge, the lifespan of a neurostimulation system can be prolonged, necessitating the development of precise charge-balancing technologies. This paper presents an 11.3V-compliant current-controlled neurostimulation circuit employing a two-step charge balancing technique. Implemented in a 180nm BCD process, the stimulator chip occupies a core area of 0.88mm². Simulations results demonstrate that the prototype can source or sink currents up to 2.5mA with a 4-bit resolution, while maintaining the residual voltage below 537μV. The proposed two-step charge-balancing technique reduces the standard deviation of the steady-state residual voltage by 95.1% compared to conventional single-step method, whereas the increased charge-balancing time is merely 1.3% at an initial residual voltage of 1V.

16:40 – A Low-Power Analog Hardware Nearest Centroid Classifier for Glioma Brain Tumor Classification

This paper presents an energy-efficient analog nearest centroid classifier tailored for real-time glioma brain tumor classification. Implemented using the TSMC 90nm CMOS process, the design leverages sub-threshold operation and custom analog architectures, including Manhattan Distance Calculation and Loser-Take-All circuits, to achieve minimal power consumption. When applied to a dataset incorporating clinical and genetic features relevant to glioma grading, the system attained an average classification accuracy of 93.62%, closely paralleling its digital counterpart. Simulation results, including Monte Carlo and PVT analyses, affirm the classifier’s resilience under process variations and environmental changes. Consuming just 542 nW and delivering robust classification rates, the proposed solution demonstrates strong potential for deployment in portable diagnostic tools and low-power biomedical systems.

17:00 – A Power-Efficient Analog Integrated Decision Tree Classifier for Dementia Prediction

An analog integrated decision tree classifier designed for real-time dementia prediction with low power consumption is presented in this work. The design uses sub-threshold analog circuitry, including a squarer circuit, analog multiplier, and current comparator, to achieve an exceptionally low power consumption of 729nW and a classification speed of 570K inferences per second. It is developed using the TSMC 65nm CMOS process. The classifier consistently performed well despite process, voltage, and temperature fluctuations, achieving an average accuracy of 90.63% when tested on a dataset representative of machine operating conditions. Through the prediction of dementia neurological disorder, this method offers effective, real-time, edge-based classification in biomedical settings.

17:20 – Double Differential Amplifier by means of a MOS CCII for Active Electrodes

This work provides a concrete implementation of the Double Differential (DD) amplifier topology, which exploits the current-mode approach to be used as front-ends in standalone active electrodes for superficial electromyography (sEMG) applications, thus, adding a novelty to currently published DD amplifiers, which only describes the advantages of using second generation current conveyors in the biomedical system.