Analog Circuits II

16:00 – A Novel 0.4-V Current-Biased Inverter-Based Two-Stage Fully-Synthesizable OTA

This paper presents a novel 0.4-V current-biased inverter-based two-stage fully-synthesizable operational transconductance amplifier (OTA), targeting ultra-low-power analog signal processing in standard-cell design environments. For the first time, a synthesizable current-biasing technique compatible with digital design flows is introduced and integrated into a two-stage inverter-based OTA topology. The proposed architecture eliminates the need for custom bias circuitry, enabling fully-automated implementation and scalability across CMOS technology nodes. Operating at 0.4-V supply and implemented in standard 180-nm CMOS technology, the OTA achieves competitive gain and bandwidth metrics while maintaining nanowatt power consumption, making it well suited for energy-constrained applications such as IoT edge nodes and biomedical interfaces. Simulation results validate the effectiveness of the proposed design, demonstrating its capability to bridge the gap between analog functionality and digital synthesizability.

16:20 – A Novel Ultra-Low-Voltage Pseudo-Dynamic Voltage Comparator Based On OAI Standard-Cells

In this paper, a novel Pseudo-Dynamic Voltage Comparator (PDVC), based on OAI (Or-And-Invert) standard-cells, with Non-Rail-to-Rail input common-mode range (ICMR) is presented. The topology exploits OAI gates to reduce the clock-to-output delay and Power-Delay-Product with respect to the other conventional Dynamic Voltage Comparators (DVCs) in literature, and, its operating principle is described in detail at transistor level. The overall performance of the circuit is assessed, referring to a 45 nm CMOS technology, considering three different supply voltages: 0.6V, 0.3V and 0.15V, along the entire input common mode range. The results demonstrate the strong advantages of the proposed PDVC, in terms of speed and Power-Delay-Product, with respect to the other conventional Non-Rail-to-Rail DVCs in literature, especially with hardly scaled supply voltages down to 0.15V.

16:40 – A 0.3V Hysteresis Comparator with Bulk-Based SRAM Output Stage

A hysteresis comparator for ultra-low-voltage asynchronous Sigma-Delta Modulators is presented, featuring a regenerative bulk-based SRAM output stage for rail-to-rail operation and enhanced speed. Simulations show a delay of 35.91µs, power dissipation of 7.27nW, and a hysteresis threshold of 4.20mV. The design exhibits strong resilience under PVT and mismatch variations. An analytical hysteresis model, validated through simulation, closely matches observed behavior. Compared to a state-of-the-art solution, the proposed comparator achieves an up to 2X faster delay, lower power, and more stable hysteresis, making it well-suited for low-power analog applications in IoT and biomedical systems.

17:00 – A CMOS Full-Wave Envelope Detector for OOK Signals in Power-Line Communication

In this paper, an envelope detector designed in a 0.18-μm standard CMOS process is presented. The proposed design is suitable for use in an OOK (On-Off Keying) receiver targeting Power Line Communication (PLC) applications. The detector is capable of tracking OOK signals with carrier frequencies equal to 10 MHz, supporting data rates up to 200 kHz. Detectable input signals span from 300 mVpp up to peak-to-peak amplitude equal to the supply voltage of 3.3 V. Performances of the proposed architecture have been evaluated through extensive electrical simulations. Robustness of the design has been demonstrated under temperature variations and in the presence of global and local random process variations, simulated through sets of Monte Carlo runs.

17:20 – A Comparative Study of Voltage Reference Generation Techniques for Low-Voltage Micropower Management Circuits

In this paper, a comparative analysis is performed between two techniques previously presented in the literature for generating voltage references (VREF), focusing on their stability with respect to variations in temperature and process parameters, in the context of integrated micropower management circuits. The first technique combines Proportional-to Absolute-Temperature (PTAT) and Complementary-to-Absolute Temperature (CTAT) currents generated with the support of operational amplifiers, to generate the VREF. The second technique utilizes a self-biased current mirror for generating a PTAT current, while the CTAT current is again generated with the previously used opamp-based circuit, and both currents are added to generate the VREF. A band-gap reference (BGR) design involves a bandgap core, a summing circuit, and a start-up circuit to apply the correct bias. Both BGR1 and BGR2 circuitry provides a voltage reference of 900mV over-40°C to 100°C temperature range with a power supply (VDD) of 1.2V.

17:40 – Robust GaN two-stage operational transconductance amplifier using dynamic voltage shifter

A two-stage GaN operational transconductance amplifier is proposed, which uses a dynamic voltage shifter based on the switched-capacitor technique to achieve robustness against process tolerances. The dynamic voltage shifter overcomes the traditional limitations of GaN transconductance amplifiers, which are due to the lack of complementary transistors and large parameter variations. Indeed, the use of n[1]channel transistors for the input pair, current mirrors, and second stage gain makes the performance of the traditional transconductance amplifiers greatly dependent on process tolerances. For circuit validation, a two-stage amplifier was designed using the traditional and proposed approach. For this comparison, the model parameters of a 0.5-µm GaN technology and a power supply of 6 V were adopted. Under worst-case process conditions, the proposed two-stage amplifier achieves a gain and a linear swing that are 64 dB and 1 V, while the traditional amplifier provides only 34 dB and a few tens of millivolts, respectively, considering a THD of -40 dB.