Analog Circuits I

Monday, September 22nd | 11:00–13:00

Session Chair

Chair: TBD

11:00 – A Fully Differential Amplifier with active load using cross-coupled bulk to enhance the gain and CMRR

Kashif Nisar, Andrea Ballo, and Alfio Dario Grasso

This paper analyzes and proposes a fully differential amplifier with PVT-compensated boosted gain. The amplifier, based on the conventional differential pair with a trimmed cross-coupled bulk active load, has been implemented and simulated in 28nm bulk CMOS technology and supplied by 0.5 V. The amplifier provides, for a quiescent current of 100 nA, a constant gain bandwidth product (GBW) of 1.3 MHz, in the worst case corners, and a differential gain and CMRR, equal to 65.59 dB and 83.28 dB, respectively. The amplifier outperforms stable features in the temperature range from 80°C down to −100°C and across the process corners.

11:20 – A Fully Differential CMOS Low-Power Low-Noise Front-end Amplifier for Impedance Measurement

Julia Aragues, Belen Calvo, and Nicolas Medrano

This paper presents the design of a fully differential capacitive-coupled/capacitive feedback low-noise preamplifier suitable for operation over the high-frequency range required by cell impedance characterization (< 1 MHz). Designed in a low-cost 0.18 um CMOS technology, it exhibits a 40 dB gain while featuring an enhanced state-of-art power-noise trade-off thanks to the use of a single-stage complementary-input cascoded-output OTA: the power consumption is 10.4 µW at a single 1.2 V supply, the NEF is 1.2 and the PEF is 1.7. Besides, its bandwidth is fully reconfigurable to optimize detection at different specific applications.

11:40 – A Spur-Reduced Power-Efficient Fully Differential VCO-based Operational Transconductance Amplifier

Kaixin Tang, Jesko Flemming, Hendrik Siemßen, Pascal Witte, and Bernard Wicht

This paper presents a spur-reduced fully differential operational transconductance amplifier (VCO-OTA). The presented VCO-OTA architectures are based on an existing architecture utilizing a combination of a phase-frequency detector (PFD) and a charge pump (CP). The architecture is enhanced by splitting the CP into three CPs without changing the total current in a time. The proposed architecture achieves a spur reduction of 13.9dB while shifting its harmonics to three times higher frequencies due to the higher interleaved clock of the output stage, causing a significant suppression of current ripples in the time domain. With a combination of the three CP blocks into a single unit, these improvements are achieved without spending significantly more power or area as compared to a state-of-the-art VCO.

12:00 – Comparative Study of Two Capacitive Isolation Information Transmission Systems

Ming Zhang, Jasper Arbois, and Nicolas Llaser

In this paper, a comparative study of two capacitive isolation information transmission systems is conducted. Previously two systems designed for an AC-switch driving were proposed. Thanks to capacitive isolation, the proposed systems are compatible not only with CMOS technology but also with strong magnetic field environment such as MRI equipment. Both systems share the same modulator but differ in demodulator: one uses an inverter-based envelope detector and the other uses a current-source-based envelope detector. The comparison is based on Monte-Carlo (MC) simulation with purpose to compare the stability of carrier frequency, of power consumption and of signal delay between the two systems. To enhance the circuit robustness against technological dispersions, improvement has also been brought to the initial systems. Both systems are designed in CMOS HV 0.35µm technology under 3.3V supplies and MC simulations are given.

12:20 – A Low-Power Analog Integrated Gaussian Function Circuit Using Source Degeneration and Adaptive Bulk Biasing for Forest Fire Prediction

Vasileios Moustakas, Vassilis Alimisis, Konstantinos Cheliotis, Anna Mylona, and Paul P. Sotiriadis

In this work, two primary methods are used to improve linearity, robustness, and adjustability in the proposed ultra-low power (2.26nW), low-voltage (0.6V) analog integrated Gaussian function circuit. It is composed of a NMOS cascode current mirror, a symmetric current correlator, and a differential pair with adaptive bulk and source degeneration. Voltage and current biasing are used to electronically adjust the height, mean value, and variance of the Gaussian function curve separately. Results from post-layout simulations are used to confirm the proposed circuit’s proper operation. The Cadence IC Suite is used for simulation and verification, and the TSMC 65nm CMOS process is used to implement the design. The circuit is evaluated as a key component in a real-world classification task and compared with related works in the literature.