RF Circuits II

16:00 – Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications

This paper investigates a multi-class, Three-Way digital Doherty power amplifier (DDPA) for Bluetooth applications, that achieves a peak output power of 20dBm, using a 0.7V supply voltage. The proposed Three-Way DDPA is made of three Switched-Capacitor Power Amplifiers (SCPAs), power combined with an on-chip Series Combining Transformer (SCT). The Three-Way DDPA is implemented in a 22nm bulk CMOS technology, with the main goal of supporting all the BT/BLE power classes, efficiently. The technique of the Dual Line Up (DLU) is leveraged to achieve good efficiencies both at low and high power. Simulation results show that the proposed power amplifier features three efficiency peaks at 0, 10 and 19.3dB Power-Back Off (PBO) with drain efficiencies of 47%, 47%, and 40%, respectively.

16:20 – A 127-163 GHz LNA with in-band 21-dB gain and 6.8-dB NF in a 55-nm SiGe BiCMOS technology

This article presents the design of a low-noise amplifier (LNA) in a 55-nm SiGe BiCMOS technology targeting high-data-rate applications. The sizing and biasing of the heterojunction bipolar transistor (HBT) are discussed and a design flow is proposed which avoids the systematic use of electromagnetic (EM) solvers. On the one hand, a parametric model for transmission lines addresses the need for design variables while having a good correspondence with EM simulations. On the other hand, a graphical method is proposed to realize a trade-off between noise and conjugate input impedance matching. A complete post-layout simulation of the LNA is performed, showing a 127 - 163~GHz bandwidth, with a maximum gain of 24~dB and a noise figure below 6.8~dB for 20-mW power consumption. Passive components such as capacitors are measured and compared to the EM simulations.

16:40 – A Novel Q-band Inductor-Less Vector Phase Shifter in 130 nm SiGe BiCMOS Technology for Active Reflective Intelligent Surfaces

This work proposes the design of a Q-band active vector phase shifter in 130 nm SiGe BiCMOS technology for active reflective intelligent surfaces. The phase shifter is based on two Gilbert cells working as variabile gain amplfiers (VGAs) for the in phase (I) and quadrature (Q) input signals. This contribution presents an inductor-less design, which allows to obtain wideband operation, greater miniaturization and scalability in relation to the technology node without using complex matching networks. Futhermore, by avoiding the use of inductors, their low quality factors no longer degrades the circuit, thus improving overall performances. The active phase shifter layout simulations are reported to evaluate the achievable results: phase shift can range up to 360°, with a conversion loss of -2.5 dB at 50 GHz and 10mW of overall power consumption.

17:00 – 2.44 GHz ISM Band LNA Front-End in 180-nm CMOS for High-Throughput IR-UWB Receivers

This paper presents the design and measurement of a 2.44 GHz common-source cascode LNA with source degeneration for IR-UWB receivers. The LNA has a 300 MHz bandwidth and is employed in the Impulse Radio Ultra Wide Band (IR-UWB) receiver front-end. The post-layout simulations show around 5 dB noise figure over the working bandwidth. The LNA is manufactured in a 180 nm CMOS process. The measured S11 varies between -10 dB and -15 dB, whereas S21 is 9.24 dB at 2.44 GHz. The time domain UWB pulse measurements are conducted with a transmitter and LNA connection through an attenuator, and a 200 Mbps operation is achieved. The total energy consumption of the LNA core is 8.44 mW, corresponding to 42 pJ/bit. When including the output buffers for 50-ohm measurements, the total consumption increases to 32.4 mW.

17:20 – An automation-oriented approach for RF/mm-Wave multi-stage LNA

This work aims to establish, from a practical point of view, the basis of a methodology to automate the design of multi-stage low-noise amplifiers (LNA). The proposal, using the g_m/I_D approach as a characterization tool for each stage, efficiently identifies the most suitable operating point according to the overall system specifications. The proposed design flow contemplates criteria to guarantee a satisfactory union between stages, allowing control of the reflection coefficients along the chain to preserve the individual performance of each stage. The effectiveness of the method is validated using a case study in which an LNA based on three source-degenerated Common-Source stages is designed, evidencing its applicability and potential for the exploration of the design space without using an electrical simulator during the design process, as in classical approaches.

17:40 – A Low-Power, Low-Noise Common-Gate LNA with Negative-Positive Feedback in FD-SOI for Harmonic Rejection N-Path Mixer Systems

This paper presents a common-gate low-noise amplifier (CG-LNA) incorporating negative and positive feedback loops, implemented in FD-SOI technology. Our CG-LNA achieves a gain exceeding 21 dB across the 370 MHz to 1.5 GHz frequency range, while maintaining a minimum noise figure of 1.7 dB and an ultra-low power consumption of 1.1 mW. The amplifier effectively drives an harmonic rejection four-path mixer, minimizing noise contributions and power overhead of the full receiver. Results confirm that the proposed LNA is well-suited for HR-NPM LNA first receiver architectures, offering an optimal trade-off between gain, noise performance, and power efficiency.