RF Circuits I

11:00 – A Comparative Analysis of 60-GHz LNAs for Low-Power mm-Wave Receivers

This paper presents a comparative analysis of 1-stage and 2-stage 60-GHz low-noise amplifiers (LNAs) in 28-nm bulk CMOS technology. The focus is on key design parameters such as gain, noise figure (NF), 3-dB bandwidth (BW3dB), and linearity. The LNAs are optimized for millimeter-wave (mm-wave) applications, exploiting a pseudo-differential topology with an integrated input balun for both electro-static discharge (ESD) protection and optimal input/noise matching, while maintaining low power consumption. The study reports a maximum voltage gain of 21.4 dB and 19.3 dB at 60 GHz with bandwidth of 2 GHz and 6 GHz for the 1-stage/2-stage LNAs, respectively. Moreover, the LNAs exhibit noise figure values of 6.3 dB and 6.9 dB, 1-dB compression point (IP1dB) of −19.4 dBm and −14.4 dBm, and total power consumption of 5.2 mW and 8.3 mW for 1-stage/2-stage configurations, respectively. These results demonstrate an effective trade-off between performance and power efficiency, highlighting pros and cons of 1-stage and 2-stage LNAs for mm-wave applications.

11:20 – W-Band Front-End Amplifiers in a 250 nm SiGe BiCMOS EPIC Technology

This paper presents a low-noise amplifier and a power amplifier for W-band applications in a silicon-photonic 250nm SiGe BiCMOS EPIC technology, with the aim of illustrating how bandwidth, noise figure and output power compare against circuits fabricated in simpler non-EPIC technologies. Furthermore, the designed circuits were also combined with a variable gain amplifier. The chips have been manufactured and characterized; the experimental results are here reported. A demonstration of these essential components for a photonic-aided wireless radio communication system in an silicon photonic technology have not yet been documented in the literature.

11:40 – A Wideband Model for a Stacked Millimeter-Wave Transformer-based Power Combiner

This paper presents a wide-band model of a transformer-based power combiner employing simple equations for coil inductances. To verify the model, electromagnetic simulations are performed on two different power combiner dimensions. The model is valid up to over 160 GHz. The power combiner studied is implemented in a 28 nm CMOS process. The equations depend on both the combiner dimensions and the technological parameters, showing good agreement between the model and the electromagnetic simulated data.

12:00 – A High-Gain, High-Efficiency GaN HEMT Power Amplifier for L/S-Band 5G Vehicle Connectivity

This paper presents an optimum high-power GaN-based power amplifier operating in the L/S-band, specifically designed for 5G-connected vehicles and IoT applications. The designed power amplifier achieves a power-added efficiency (PAE) of 65% across a bandwidth ranging from 1.8 to 2.3 GHz. The architecture consists of a configuration employing Class-F amplifiers, utilizing the Cree CG2H40010F GaN HEMT device. Simulation results demonstrate that, with a drain voltage of 28 V and a quiescent current of 100 mA, the amplifier delivers an output power of 20 W, a gain of 18 dB, and maintains a high PAE of 65%.

12:20 – A 5.4 mW K-Band LNA with 1.9 dB Noise Figure for Radar Applications in 90 nm BiCMOS

This paper presents a very low power LNA designed and manufactured in a 90 nm BiCMOS technology. The transistors were dimensioned to obtain both low-power and low-noise design. The chip was measured on-wafer by probing. The LNA operates around a center frequency of 19 GHz and provides a power gain of 14 dB, while achieving a low noise figure of 1.9 dB. A high input-referred 1dB linearity of -7 dBm was measured. The fully differential chip consumes 5.4 mW from a single 1.8 V supply and takes up an area of 0.43 µm².

12:40 – A DLL-Based FSK Demodulator for Asynchronous Communications

This paper discusses the use of a delay-locked loop (DLL) to perform frequency shift-keying (FSK) demodulation in asynchronous communication systems. Instead of being part of a more complex architecture, the DLL is here used as a frequency demodulator. Similarly to its phase-locked loop (PLL) counterpart, the DLL-based FSK demodulator tracks the frequency variations of the input signal, providing at the output the demodulated received data. The DLL constitutes an efficient alternative to the PLL for FSK demodulation due to its lower complexity, moderate power consumption, and reliable performance even in the absence of a reference clock. The viability of the DLL as FSK demodulator is verified by means of both behavioral and transistor-level simulations carried out in a 0.13μm CMOS technology.