CAD

15:00 – On Time-Interleaving Errors in Beamforming Receivers

Time-interleaved ADCs are a key building block in mm-wave receivers, where the use of multi-GHz signal bandwidths requires high-performance wide-band data conversion. It is therefore necessary to explore the beamforming receiver system impact of different time-interleaved ADC parameters and limitations, such as number of interleaved channels, mismatches between channels, nonidealities of the sub-ADCs, and correlation between sub-ADCs. This paper presents a scalable testbench in MATLAB/Simulink which models time-interleaved pipeline ADCs with high fidelity. The testbench is used to investigate the impact of time-interleaving errors on digital, hybrid, and analog beamforming receivers, both with and without interfering signals. Results show that the combination of time-interleaving errors and interference causes a degradation in beamforming performance, even at relatively low SNDR levels. The effect is more pronounced in digital beamforming compared to hybrid and analog beamforming.

15:20 – Automatic Generation of ACM Design-Oriented Models for MOS Transistors from Quasi-Static Wafer-Level Characterization Data

This paper introduces a novel MOS Transistor model extraction methodology from wafer-related parametric test data to characterize process variation effects. This approach provides critical insights into the impact of variability on devices after production and supports a more efficient and comprehensive design process by enabling circuit post-fabrication simulation and calibration. By identifying performance variation causes at the transistor level, the application of this method to performance prediction represents a major advancement over existing post-fabrication simulation approaches, enabling potential improvements in production yield.

15:40 – A Matlab-Spectre Toolbox for Automated Design of Ultra-Low Power CMOS Voltage References

This paper presents a Matlab-Spectre toolbox for the automated design of ultra-low power (ULP) CMOS Voltage References (VRs). The tool, developed to support circuit designers, allows for a quick exploration of the design space and it returns the sizes of the devices in the circuit for the best temperature coefficient and spread over corners. Our toolbox is compatible with multiple process design kits (PDKs), for fast porting of reference designs across different technology nodes. In this paper we report on the automated design of an enhanced 4T-VR using our CAD toolbox. The design achieves a spread over corners of 1.8% and a temperature coefficient of 32 ppm/°C.

16:00 – Transistor-Level Simulation for Neural Network Analog Implementations

This paper presents an integrated simulation framework for mapping neural network models onto analog circuits, enabling energy-efficient inference. Our method automatically converts weights and activations into electrical parameters, generates SPICE-compatible PWL files, and simulates analog crossbar arrays implementing MAC operations with foundry-approved simulators and PDKs. We validate our approach using a bulk-modulated PMOS analog MAC cell in two applications: a single-layer network for MNIST classification and a CNN for CIFAR-10 classification.

16:20 – Optimizing Standard Cell Design Using Particle Swarm Algorithm: Evaluating Post-Layout Results

Standard cells are widely used in modern VLSI electronic circuit design. Optimizing their performance significantly enhances the performance of the final circuits. However, the number of requests for new libraries of standard cells is on the rise, for increasingly complex technology nodes and with a continually shortening time-to-market. One way to optimize performance without increasing a designer's workload is to delegate it to an algorithm. The design space of a standard cell can have few to many dimensions depending on the number of transistors, making exploration a complex challenge. As performance is measured through electronic simulations, obtaining the gradient can be complex and methods that do not require it are preferred. Particle swarm optimization, based on behavioral models, does not need a gradient, as it explores a large space by dispatching and moving particles inside this space. In this work, the standard cells design space is explored by the particle swarm algorithm to find the optimal performance. The obtained parameter set is used to design a new layout and evaluate post-layout performance. Finally, the performance of the new layout is compared to the original one and to the results of the optimization.