ADCs

16:00 – An 8-bit 10MS/s C-2C Charge-Sharing SAR-ADC

A C-2C Charge-Sharing (CS) SAR-ADC is proposed in this work. The binary-weighted charges result from the scaling of the voltages at the capacitors terminals, instead of the capacitance scaling. This is achieved using a C-2C ladder topology, in which, only C and 2C capacitance values are used. During the conversion phase, the cells of C capacitors are added one by one to the comparator’s input to perform the quantization with the respective weights in the charge domain. The C-2C ladder ensures a constant input capacitance of 2C, which allows significant energy savings from an on-chip reference buffer. The digital-to-analog (DAC) scales linearly with the number of bits, contrary to the exponential behavior of the binary-weighted counterpart. This facilitates dealing with the comparator’s offset voltage-induced charges. An 8-bit, 10 MS/s C-2C CS SAR-ADC was designed as a proof of concept using a standard 28 nm bulk CMOS technology, achieving an effective number of bits (ENOB) of 7.81. To the best of the authors’ knowledge, this represents the first CS SAR ADC architecture that employs a C-2C DAC structure.

16:20 – A 2.5 GS/s 8-bit Burst-Mode Noise-Shaping SAR ADC for Monitoring Switching Transitions in Digital Gate Driving Applications in 180nm HV-SOI CMOS

This paper presents a 2.5 GS/s burst-mode noise-shaping SAR ADC monolithically integrated with a digital gate driver circuit for wide-bandgap power transistors in a 180 nm HV-SOI CMOS technology. The converter is used to monitor the terminal voltages of an external wide-bandgap power transistor during switching transitions. To capture the fast transient switching waveform, the converter needs to operate at a very high sample rate. On the other hand, the time between switching events does not contain any information. This motivates the use of a burst-mode converter, where a parallelized sampling stage captures samples during a short burst, which are then subsequently converted during the idle period between switching events. The implemented burst-mode sampling stage captures 32 samples with a maximum sample rate of 2.5 GS/s, which are then sequentially converted by a noise-shaping SAR core with a nominal resolution of 8 bit.

16:40 – Analysis of the Input Resistor Thermal Noise in High Precision Hybrid CT-DT ΣΔ ADCs

This paper investigates the impact of the input resistor thermal noise in high-resolution hybrid continuous-time/discrete-time (CT-DT) Σ∆ analog-to-digital converters (ADCs), with particular emphasis on the co-design of the input buffer and the ADC front-end. Targeting Industry 4.0 sensor interface applications, where accuracy and power efficiency are critical, this work addresses how the thermal noise originating in the CT stage limits the system signal-to-noise-ratio (SNR). A modeling strategy for this noise contribution is introduced and validated through Simulink® simulations, using a colored-noise approach, enabling a realistic spectral representation and accurate performance prediction. The proposed architecture, a third-order hybrid cascade-of-integrators-with-feedforward (CIFF) Σ∆ modulator, demonstrates compelling trade-offs between resolution, power consumption, and area. The adopted design choices are guided by analytical insights into integrator gain, RC time constants, and their effect on SNR performance. Simulation results confirm the effectiveness of the proposed approach, showcasing a 111.7-dB SNR with a 0.8-V input signal, at a 10.24-MHz sampling frequency.

17:00 – A Generalized Design Methodology for Band-Pass ΣΔ Modulators

This paper presents a methodology for the design of band-pass ΣΔ modulators. The proposed procedure does not force the modulator central frequency fn to one quarter of the sampling frequency fs (or to one of its odd multiples), nor imposes each resonator to have an order higher than 2, as a 2-path and an N-path transformation would respectively do. Starting from the synthesis of the noise transfer function (NTF), which can be accomplished using some MATLAB functions, it is possible to derive the transfer functions of the resonators making up the modulator. To validate the proposed methodology, this paper also illustrates the design of a 4th order band-pass ΣΔ modulator having a 400-kHz central frequency, a sampling frequency of 6.4 MHz and OSR equal to 160, used to drive an ultrasonic transducer and achieving a dynamic range of 72.5 dB.

17:20 – Parallel TIADC calibration for intermittent signal conversion

This article presents a time-interleaved analog to digital converter (TIADC) architecture that parallelizes foreground calibration and signal conversion. This architecture enables continuous calibration for TIADC sampling intermittent signal. This architecture uses two identical TIADC both sampling in parallel. A TIADC samples the signal while the other samples a calibration signal. Every analog to digital converter (ADC) alternately receives the calibration signal and the input signal. An input switch circuit in front of every ADC select the appropriate input signal. A rotational switch scheme ensures a common reference between the two TIADC. After global estimation is performed, mismatch correction is applied and the switch scheme restarts. A performance evaluation of a 2.5-GS/s 11 bit 10x-interleaved ADC based on 28 nm FDSOI technology achieves a SNDR/SFDR of 64.01/78.26 dB at 700MHz after skew mismatch calibration.

17:40 – A Low-Distortion Adderless Zero-Time Reset Incremental Delta-Sigma Analog-to-Digital Converter

This work presents a low-distortion adderless switched-capacitor (SC) incremental delta-sigma modulator (I-∆ΣM), where the reset in the SC circuit is applied for half a cycle, thereby achieving a zero-time reset from a system perspective. It is derived that the adderless low-distortion path is maintained as it effectively becomes an SC-adder path directly following the reset. The key innovation of this work lies in the combination of the adderless topology with the zero-time reset, along with the derivation of the inherently higher bandwidth of a half cycle reset system. In contrast to state-of-the-art (SOTA) I-∆ΣM designs, which predominantly implement a full cycle reset, the zero-time reset yields valuable bandwidth. By means of a 2nd-order architecture, it is shown that the bandwidth increases by 12.5% at an oversampling ratio (OSR) of 8, while achieving nearly identical resolution. The concept is verified by simulation in a 55nm CMOStechnology. It is shown that neither the transmission gates nor limitations in the amplifiers impede the settling of the reset, which proves that the zero-time reset can be implemented in most SC-I-∆ΣMs designs to increase the bandwidth.