|Monday, June 19th|
|11:20-13:00||A1 | RF Circuits and Systems I|
Chair: Piero Malcovati
A 0.13µm GaAs HEMT Reconfigurable Balance-to-Doherty Stacked Power Amplifier for 5G mm-wave Applications
This paper presents a reconfigurable Doherty-tobalanced (D2B) power amplifier (PA) operating in the Ka band for 5G applications. The circuit, designed in a 0.13µm GaAs HEMT technology, uses a single-pole-double-throw (SPDT) switch that can enable the reconfiguration between a 50Ohm and a short. The PA achieves a peak power added efficiency (PAEsat) of 21.7% at a saturated output power (Psat) of 28.5dBm in the Doherty mode and 31.4% PAEsat with 29.6dBm Psat in balanced mode. The balanced PA offers good immunity to load mismatches up to a 3:1 VSWR achieving output power fluctuation within 3 dB.
Switching Mode Power Amplifier for Fully Digital RF Transmitter at 3.6 GHz in 22 nm FD-SOI CMOS
Post-layout simulation results of a current mode switching mode power amplifier (CM-SMPA) in 22 nm FD-SOI CMOS for a fully digital RF transmitter with a peak output power of 23.51 dBm (224.4 mW) at 3.6 GHz are presented. The CM-SMPA is driven by a pulse-width (PW) and pulse-position (PP) modulated signal for amplitude and phase control. To increase the amplitude dynamic range, the conductance (G) of the switches is also modulated. For a 64-QAM signal with 112.5 MBd, an error vector magnitude (EVM) of -32.50 dB with a maximum adjacent channel leakage ratio (ACLR) of -40.81 dB in the neighbor channel is achieved. The average total efficiency and drain efficiency are 24.93 % and 32.12 % respectively. The large signal bandwidth potential of this transmitter concept is shown by a simulation of a 450 MBd 64-QAM with a channel bandwidth of 675 MHz.
Improving Performance of InGaP/GaAs HBT Arrays by means of Temperature-Dependent Base Ballasting Resistors
Base ballasting resistors (BBRs) are commonly adopted to minimize electrothermal (ET) effects in arrays of bipolar transistors for power amplifier (PA) applications. In this paper, innovative BBRs with temperature-dependent resistivity are proposed in order to improve the trade-off between safe-operating area (SOA) and radiofrequency (RF) performances. As a simple case-study, a three-cell heterojunction bipolar transistor (HBT) fabricated by Qorvo is considered and circuital ET simulations are performed in ADS. Results of the comparison between the proposed strategy and the traditional one are discussed, thus providing useful insights into the advantages of temperature-dependent BBRs.
A mmW RadCom System for Short-Range Hand Gesture Sensing and Data Synchronization
A multifunctional transceiver for radar sensing and wireless communication (RadCom) has proven to be a valuable alternative to single-function transceivers as it enables system miniaturization and cost reduction. The use of a RadCom system for hand gesture recognition and data synchronization in smartphones could further advance smartphone development to attain another level of miniaturization. However, power consumption remains a significant concern in these applications. This paper presents a low power RadCom architecture based on a 1-bit comparator, for high resolution sensing and high data rate communication. The transmitter is able to generate IR-UWB pulses and ASK symbols. The simulation results show that data transmission can be implemented up to 5 Gbps and within a range of a few cm. The results also show that the 1-bit comparator architecture can identify three out of five fingers of the hand and accurately translate the propagation channel scenario into the range Doppler map (RDM).
Area-Efficient and Wideband Input Stages for SiGe BiCMOS G-Band LNAs
Simultaneous wideband input matching and gain performance while maintaining low core area is one of the big challenges of mmW amplifier design. In this work, the stacked common base (stacked CB) configuration is proposed for the input stage of an amplifier to achieve a good compromise between gain, input matching and area. To prove its validity, the stacked CB topology is compared with the cascode and simple CB configurations. Finally, two G-Band amplifiers are designed with different input stage topology: cascode and stacked CB. Both show very small core area (0.066 and 0.085 mm2 respectively) while maintaining gain, NF and GBW product performance comparable to the SoA. The stacked CB version shows a wideband input bandwidth of 76 GHz (S11<-10 dB), making it a very suitable choice for area efficient and broadband input stages.
|11:20-13:00||B1 | Comparators |
Chair: Franco Maloberti
A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates
In this work a novel ultra-low voltage, ultra-low power fully synthesizable comparator is presented. The proposed architecture exploits only 2-input NAND gates, that allow minimization of the area footprint and scalability up to extremely low supply voltages. An extensive simulation campaign in a 130 nm CMOS technology has shown state-of-the-art performance in terms of power-delay-product for supply voltages down to 0.3V. Simulations also show good robustness under mismatch and PVT variations, proving the feasibility of the approach.
Robust body biasing techniques for dynamic comparators
Forward body biasing (FBB) is among the simplest and most effective techniques that can be leveraged to improve the performance of dynamic comparators, as previous works have demonstrated. However, none of them puts emphasis on comparing different FBB schemes and their robustness against large differential input swings. This is especially important when considering circuits that operate at supply voltages above 0.5 V, where several approaches can be adopted for biasing the substrates without causing the body-source junctions to turn on. This paper compares three different techniques: the clocked FBB (CFBB) proposed in , an improvement of CFBB and a new hybrid approach that achieves the best performance in terms of delay. For the sake of brevity, the scope of our experiments has been limited to the Strong Arm latch. All simulations were performed in a 55 nm CMOS technology at 1 V supply and 2.4 GHz clock frequency.
Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology
This paper presents the analysis and design of a two-stage low power comparator suitable for high-speed applications. The proposed consists of a two-stage preamplifier and a latch. The entire structure works in two phases: a reset and an operating period, which is further divided in two time-intervals: integration and latching. This comparator, designed in a 5nm FinFET technology, will be compared to the state-of-the-art implementations in 5nm FinFET technology, showing noise and charge minimisation for a given decision time.
Minimizing Quiescent Power in a Dynamically Biased Comparator and its Application in Relaxation Oscillator
This paper presents a dynamically biased, high-speed comparator architecture consuming a very low quiescent power. In conventional comparator topology, there is an underlying trade-off between the speed and the quiescent power consumption. The proposed comparator adopts a dynamic current boosting mechanism that momentarily provides a large amount of quiescent current near to the comparison point when both inputs of the comparator are getting close to each other. However, when those input voltages are widely separated, the proposed comparator enters to a low current state where the excess dynamic current has been reduced to minimize the quiescent power. To appreciate its benefits, a relaxation oscillator has been developed using the proposed comparator, targeting a nominal frequency of 1 MHz in 180 nm CMOS process. The simulation result shows that the quiescent power consumption of the proposed comparator has been decreased by ~6X as compared to the conventional fixed biased comparator while maintaining the same speed of operation. The quiescent power consumption of the relaxation oscillator has been decreased by >11X using the proposed comparator compared to the conventional one. This proves the effectiveness of the proposed technique.
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing
In this paper a novel 0.6 V dynamic biased, body driven Strong Arm latch is presented. The proposed topology exploits a charge pump based dynamic biasing configuration that boosts the effective supply headroom. In addition, the body terminals are used to drive the input pair while the gates are driven by the clock signal to allow for the removal of the tail transistor, resulting in larger peak currents and smaller parasitic capacitances. This reduces power consumption and delay. Moreover, the body driven approach enables rail-to-rail input common-mode range (ICMR). As a result, the proposed topology is capable of high-speed operation (up to 2.5 GHz) despite the low supply voltage. At 2.5 GHz the comparator shows a competitive energy-delay product (EDP) of 2.98 fJ/GHz.
|11:20-13:00||C1 | Automotive Circuits |
Chair: Alberto Gola
A 21kHz Phase Boost through Split & Filter Loop Stability Optimisation in Automotive Current Limitation
In Active Current Limiter for High-Side (HS) circuits adopted in Automotive applications stability is strongly affected by Short Circuit (SC) cases. Such several possible SC cases depend on the specific SC situations occurring in the system and, then, present different electrical conditions, for instance with inductive load from 0µH to 20µH. These SC events result in large load current step producing large current overshoot, which could damage the overall system. In this paper a simple and extremely efficient solution (namely the Split & Filter (S&F) technique) allows to limit the overshoot during transient response for all the SC events. The technique is applied to a 350nm BCD implementation and experimentally demonstrates that for the most critical cases (i.e. with the lowest Phase-Margin) PM increases from 44° to 57° reducing overshoot from 61% to 30% and decreasing peak current value, from 38.7A to 29.5A, without overcompensating the less inductive short-circuit cases. Technique robustness is validated by extended simulations with PVT corners settings.
RF Solder Ball Break Detection in Automotive FMCW Radars Using Isolated Targets' Phase
Embedded wafer level ball grid array (eWLB) packaging is a common technology for radar transceiver monolithic microwave integrated circuits (MMICs) in the automotive radar industry. One of the challenging issues with the eWLB packages is the radio frequency solder ball breaks (BBs), due to its adverse effects on the radar performance. In this paper, a method for BB detection (BBD) based on digital signal processing is proposed. This method exploits the collected data from the environment during the sensing task of the radar receiver to detect BBs in real-time. To the best of the authors' knowledge, this work is the first one that addresses the BBD problem solely by digital signal processing, meaning that no additional analog hardware is required for the detection. To validate the performance of the proposed method, simulation results for measured radar data are provided.
An Asynchronous Constant Toff, 10 A, Buck Converter with Peak Current Mode Control for Automotive Applications
In recent years, in the automotive sector, devices that need a regulated DC supply voltage have increased. DCDC switching converters are the best solution in terms of performance, cost, and efficiency. Among DCDC converters, the Step-Down switching converter (or Buck converter) is very important. The high number of these devices installed on a car requires the reduction of the cost for the system, with a very simple implementation, but maintaining comparable performances with a more complex and expensive design. In this article, an Asynchronous Constant Toff Peak Current Mode Controlled (PCMC) Buck converter, with a maximum output current of 10 A, is presented. Thanks to this type of Pulse Frequency Modulation (PFM) control and an integrated high-side current sensing, it is possible to realise an efficient system with over-current protection, duty cycle greater than 50%, without slope compensations, and high efficiency also at low loads. The implementation of the integrated current sense, the high switching frequency and the high stability of constant Toff reduce at the minimum the number of external components and the used area for IC to lower the price of the buck converter system. The Quasi-Constant switching frequency allows using a cheapest filter for automotive EMI tests. The system works with a switching frequency around 1 MHz with a precise output voltage from 1.8V to 5V with an output current up to 10 A.
A 0-360° phase shifter for 77-GHz automotive radar sensors in 28-nm FD-SOI CMOS technology
This paper presents a phase shifter in a 28-nm FD-SOI CMOS technology, which is suitable for automotive radar sensor applications in the 75-81 GHz band. The circuit exploits a switching vector modulator solution, which allows high phase accuracy to be achieved. Indeed, RMS phase and gain errors are as low as 2.2° and 0.14 dB, respectively. This performance is provided with a 1-V supply voltage and a low power consumption of 9 mW.
Control Circuits for Adjustable Digitally Programmed DC Power Supplies
This paper presents and compare two methods for digital output programming and regulation of Switched Mode Power Supplies. One method is based on shunt regulator TL431 emulation, while the other uses injected current into the reference resistor divider. Both methods are tested on LM3481-EVM commercial module and have shown good linearity and satisfactory control performances on output voltage regulation. Finally, control accuracy of the two methods is discussed.
|15:00-17:00||A2 | Analog Circuits |
Chair: Giuseppe Ferri
A Compact All-MOSFETs PVT-compensated Current Reference with Untrimmed 0.88%-(σ/μ)
An excessive sensitivity to PVT variations may represent a considerable issue of a Current Reference (CR) circuit, possibly resulting in poor reliability of CR-supplied systems. CR area occupation is also critical in size-constrained designs. In this work, we present and analyze a compact all- MOSFETs CR topology. Implemented in 0.18 μm CMOS, the proposed design generates a 946 nA reference current. Simulated temperature coefficient and line sensitivity are equal to 318 ppm/°C and 5.12%/V, respectively. Besides, based on process sensitivity analyses, the reference current exhibited a relative standard deviation equal to 0.88%, which is competitive with state-of-the-art solutions.
A Novel High-Performance Parallel-Type Slew- Rate Enhancer for LCD-Driving Applications
In applications requiring fast driving of large capacitive loads, such as LCD-driving, amplifier design is bound to implement Slew-Rate Enhancement (SRE) techniques. In this work, we investigate performances of a single-stage amplifier coupled with a parallel SRE circuit. Operating versatility and design simplicity make the parallel SRE approach noteworthy, since such features are not always guaranteed by previously proposed solutions. An improved version of an existing parallel SRE architecture is presented and thoroughly examined, through electrical simulations of a 0.18 μm CMOS design. Rail-to- rail driving capability of a 1 nF capacitive load was assessed. Slew rate and 1%-settling time equal to 752 V/ms and 4.69 μs, respectively, were obtained with a 4 μA total quiescent current. Such preliminary results confirm the proposed approach to be a viable solution for low-power high-speed amplifier design.
Noninverting Schmitt Trigger Circuit with Improved Hysteresis Behavior
This work brief a noninverting Schmitt trigger circuit with improved noise immunity. The work integrates the investigation of the proposed dual threshold controlled Schmitt trigger (DTC-ST) in terms of low switching power consumption, less propagation delay, and reduced leakage power. Thus, the end result of the proposed DTC-ST yields well-defined hysteresis behavior and better noise immunity due to the use of one PMOS and one NMOS as a two-layered feedback approach which can be employed in the low-noise receiver and waveform reshaping circuit applications. The DTC-ST has 2.89×, 1.64×, and 4.9× less delay, dynamic power, and leakage power respectively in comparison to the conventional Schmitt trigger. Further, 5000 Monte Carlo simulations reveal that low variation in VLH and VHL of the proposed circuit makes it a robust design.
15 nA CMOS Analog Voltage Buffer Insensitive to PVT Variations
An ultra-low current CMOS analog voltage buffer for use in conjunction with a voltage reference circuit is described. Despite the fairly standard topology, this study demonstrates that subthreshold operation with proper transistor sizing provides buffer performance that accurately matches that of the reference voltage circuit driving the buffer. In this way, there is no appreciable deterioration in terms of insensitivity to process, temperature, and supply voltage variations for the entire buffered reference voltage. The buffer consumes 15 nA of standby current and is able to drive a 20-pF load with a nominal open-loop gain greater than 100 dB, ensuring a closed-loop accuracy better than 0.01%. The buffer works properly under a supply voltage ranging from 1.2 V to 5 V. Moreover, under a 3-V supply, the mean value of the buffered voltage is 405.65 mV with a standard deviation of 7.44 mV in the temperature range of 40°C to 125 °C.
A compact bidirectional reconfigurable 2nd-order low-pass filter for 5G FR2 applications
This paper presents a novel architecture of a second- order bidirectional low-pass filter (LPF) and compares it with its conventional – unidirectional – version. In phased array systems, both of reception (RX) and transmission (TX) chains are physically separated in order to work alternatively – they operate in time division duplexing (TDD). Hence, each baseband analog LPF is usually alternatively addressed with switching components to operate depending on the selected mode. By doing so, the silicium is not efficiently used – when a given filter operates, the other is turned off. To address this issue, bidirectional archi- tectures seem to be perfect candidates. They guarantee bilateral operation mode sharing the same electrical nodes. A bidirectional filter was designed in GF 22nm FD-SOI (Fully Depleted Silicon- On-Insulator). It exhibits -0.54, -0.58, -0.69 and -0.9dB in-band gain over infinite loading, depending on the chosen bandwidth (BW) configuration (50-100-200 and 400MHz respectively), has a DC power of 3.64mW, an input compression point (ICP1) of -8.67dBm and an input third-order intermodulation product (IIP3) of 7.58dBm and occupies a silicium area of 0.0055mm2.
A 560 MHz Frequency Multiplier Employing a Novel Pseudo-Differential Charge-Pump PLL
This paper presents a frequency multiplier employing a pseudo-differential charge-pump phase-locked loop (PDCPPLL) and a novel technique to maintain the 50% duty cycle at the output. A differential charge-pump PLL offers common-mode noise reduction and alleviates unwanted secondary effects encountered in the single-ended architecture. Pseudo-differential PLLs do not involve common-mode feedback. Moreover, compared to single-ended counterparts, they offer improved noise suppression and leakage cancellation at the input of a voltage-controlled oscillator. A complete overview of the design will be provided along with simulations to prove its functionality and provide its sensitivity to process and temperature variations. The frequency multiplier is designed in 180 nm complementary-metal-oxide-semiconductor technology to operate at 560 MHz.
|15:00-17:00||B2 | Photon and Particle Detection Circuits |
Chair: Edoardo Bonizzoni
A 60 µW front-end for 10 ps resolution monolithic pixel sensors in a 130nm SiGe BiCMOS process
This paper presents the development and optimization of a front-end circuit and the design of a monolithic sensor demonstrator with a high spatial resolution (hexagonal pixels with 50 μm pitch) and sub-10 picosecond timing capability for the detection of ionizing radiation. The system combines a monolithic sensor in a SiGe BiCMOS process with a front-end architecture based on a SiGe Heterojunction Bipolar Transistor (HBT). The design of the prototype has been optimized to achieve improved timing performance while maintaining low power consumption by analyzing the trade-off between sensor input capacitance and power consumption. The goal is to achieve a timing resolution below 10 ps, a significant improvement over the previous prototype, which demonstrated a time resolution of 20 ps. This prototype has been developed in the framework of the MONOLITH H2020 ERC project.
A Scalable Frame-Based Readout Architecture for Monolithic Pixel Detectors with Local ADC and Time Digitization
This paper proposes a novel readout architecture for monolithic pixel sensors for photon and particle detection, capable of handling event rates on the order of tens of kilohertz, while maintaining high timing resolution and energy deposition measurements. An ideal approach providing a local measurement unit for each pixel is not feasible, due to increased junction capacitance, potential crosstalk, and higher power consumption. An intermediate solution involves a scalable and versatile ar- chitecture with a local ADC integrated outside the pixels, but within the active matrix area. Pixels are organized in a macro block, ”super-pixel”, that acts as a standalone data processing unit, and sends data on a serial bus at 200 MHz. The integration of multiple super-pixels in parallel optimizes readout time for larger matrices, thanks to a distributed digital logic and local charge measurement. This architecture has been applied to the development of the ASIC in a 130 nm SiGe BiCMOS technology for the FASER pre-shower detector at CERN, proving this concept on silicon. Overall, this novel readout architecture is a promising solution for fast pixel detectors requiring high rates, making it suitable for a wide range of applications, including particle physics and technologies based on photon detection.
8-Channel Time-of-Flight Single-Photon Detection Module Based on InGaAs/InP SPAD Array
We present the design and characterization of a complete and standalone single-photon detection module based on an array of 8 × 1 InGaAs/InP single-photon avalanche diodes (SPADs), coupled with a custom readout integrated circuit with gating capability and 8 independent time-to-digital converters (TDCs) for time-interval measurements. Each pixel features an InGaAs/InP SPAD coupled to a picosecond-resolution TDC, with an overall timing jitter of less than 200 ps (FWHM) at 5 V excess bias and 250 K. A secondary peak appears in the temporal response when more than one pixel is turned ON due to optical crosstalk phenomena, which will be minimized with further processing steps.
65 nm CMOS 8 mV/fC, 14.6 ns Rising Time Analog Front-End for ATLAS Muon Drift Tubes Detectors
This paper presents an ultra-low power, area efficient 4-channel front-end electronics for Muon Drift Tubes at Atlas Experiment. The proposed Analog Front-End is composed by low-noise Charge Sensitive Preamplifier (for charge-to-voltage conversion), a continuous-time Shaper/filter for Bipolar Time- Domain Pulses feeding a dynamic (no-clocked) Comparator (for voltage to time conversion). The system is designed to detect an input charge in the range of 5-100 fC. The peaking time delay of Analog channel is 14.6 ns and exhibits a sensitivity of 8 mV/fC. The design has a single mode of operation, time-over-threshold. At the output the ToT encoding of input charge is provided in low-voltage differential signal, for connecting with TDC board, along with digital CMOS level signal. The design is operated from a single 1.2 V supply voltage. The chip is realized in 65 nm CMOS technology and has a total area occupancy of 4 mm2.
Monte Carlo simulations of Fully Depleted CMOS pixel sensors for radiation detection applications
The ARCADIA (Advanced Readout CMOS Architectures with Depleted Integrated sensor Arrays) collaboration has developed 25 μm pitch Fully Depleted Monolithic Active Pixel Sensors (MAPS) based on a modified 110 nm CMOS process in collaboration with LFoundry. This work illustrates a set of simulations performed on this detector technology, with the aim of investigating its capabilities for radiation detection applications. Three-dimensional Technology Computer Aided Design (TCAD) simulations have been performed in order to extract the electric field and electrostatic potential maps suitable to execute Monte Carlo simulations, providing high statistics of particle-sensor interaction in a reasonable computing time. The simulation flow will be described in detail and the main results will be pointed out.
Charge Sensitive Amplifiers with Bi- and Trilinear Signal Compression Feature for LGAD Detectors
This work is concerned with the design of Charge Sensitive Amplifiers (CSAs) featuring dynamic signal compression. Two different CSA variants have been developed to reach low-noise performance while dealing with signals covering more than three decades in dynamic range. The CSAs have been designed in a 65 nm CMOS technology as part of the front-end circuit for the read-out of upcoming Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The paper will discuss the proposed CSA architectures, and the relevant simulation results.
|15:00-17:00||C2 | Sensing and Biomedical Circuits |
Chair: Virgilio Valente
Oscillator Based Bio-Sensor for Skin Sweating Detection: A Feasibility Survey
This paper is a feasibility survey of the design of an oscillator-based bio-sensor for skin physiological parameter detection. The sensor aims to detect stress through skin sweating measurement. The proposed architecture uses an oscillator coupled to an on-skin resonator. The oscillator is based on a cross coupled pair (CCP) which is directly connected to the resonator. The on-skin resonator has been designed to have an oscillation frequency sensitive to the sweat. Oscillator outputs are driven by two buffers that act as 50 Ω impedance matching. Two test benches, one with a dry skin and one with a wet skin, have been used for the study. The oscillation frequency of this oscillator is equal to 27.876 GHz for the dry skin, and 27.911 GHz for the wet one. The difference between the two oscillation frequencies, which is equal to 35 MHz, can be easily distinguished which validates the feasibility survey. The survey provides the sizing of each block and the simulated results in 55 nm BiCMOS technology.
56-MHz-Bandwidth 2.4-3.5 μV/Pascal-Sensitivity- Range Polyvinylidene Fluoride Ultrasound Sensor Array for Biomedical Thermoacoustic Imaging
In this paper the design of broad band Polyvinylidene Fluoride (PVDF) based piezoelectric ultrasound transducer is presented. A Finite Element Model (FEM) is used to simulate here PVDF ultrasonic transducer. Based on this FEM, relationship between Physical structure and properties of PVDF transducer are studied both in simulation and experiment. It shows that the center frequency and many other property parameters of PVDF ultrasonic transducers are strongly related to the physical structures of it. Finally simulation result shows the resonant frequency of (54MHz) and sensitivity of (3.6 uV/Pa). A prototype multi-channel arrays 0.3mm x 10mm active area has been fabricated and experimentally validated its preliminary results in terms of electrical and acoustic properties.
A Time-Based CMOS Readout Circuit for Amperometric Biosensors
Miniaturization of electrochemical sensing devices for point-of-care, wearable and implantable diagnostics relies on CMOS potentiostat readouts that offer rapid and accurate test results. Conventional CMOS potentiostats are based on traditional analog blocks such as op amps and comparators, with a performance penalty in terms of power consumption and dynamic range. Time-based readout architectures offer unique advantages to achieve ultra-low power and low voltage operation without sacrificing small area and resolution. In this paper, we present the design of a CMOS potentiostat circuit with a current-mode time-based SAR ADC readout. The simulated results suggest that the readout channel can achieve an estimated energy efficiency of 1.5 pJ/bit from a 1.8 V supply. The proposed architecture can be readily scaled and programmed for a wide range of input currents, which makes it suitable for multiplexed multi-analyte systems.
A Sustainable Printed Chitosan-Based Sensor for Acetone Detection
Biomedical sensing applications, including breath analysis, contribute to increasing the amount of electronic waste, as the sensors are frequently disposed, due to hygienic considerations. Consequently, the development of sustainable sensor solutions is crucial. Here, a Chitosan-based sensor proposed for the utilization in biomedical applications is presented. The sensor is fabricated on a bio-sourced and biocompatible thermoplastic polyurethane substrate, and its response to Acetone vapor is studied. The use of Chitosan, a natural biopolymer, together with additive manufacturing technologies make this sensor sustainable, while the use of biocompatible materials makes it well-suited for biomedical applications. The sensor shows a good linearity in the range between ambient Acetone concentrations of 0 - 73 ppm with relative changes of 0.42% per ppm and 2.75% per ppm at ambient humidities of 50±5%rH and 80±5%rH, respectively.
A 0.26 dB Noise-Figure 2.4 mW-Power Low-Noise-Amplifier with Auto-Tuned Pseudo-Resistors for Ionoacoustic Range Verification
Ionoacoustic detectors sense the weak signal emitted by the fast energy deposition of a proton beam through the energy absorber and exploit this detected signal to spatially measure the beam penetration depth or range, with promising application in hadron therapy treatment monitoring. However, clinical scenarios exhibit very weak acoustic signal power (tens of mPa) in 10 kHz - 1 MHz bandwidth. Therefore, it is of fundamental importance that the front-end amplifiers operate at very low noise levels (few nV/√Hz of in-band noise power spectral density) to minimize the degradation of the Signal-to-Noise Ratio (SNR). The Low-Noise-Amplifier (LNA) proposed in this paper operates in such a critical scenario, exploiting an advanced and dc-stable pseudoresistor implementation to minimize noise power, achieving 0.26 dB of Noise Figure. The LNA has been designed in 28 nm CMOS technology, has a passband gain of 30 dB, an integrated noise power in the ionoacoustic bandwidth of 7.5 μVRMS and 2.4 mW power consumption.
|Tuesday, June 20th|
|11:20-13:00||A3 | Radio Frequency Circuits and Systems II |
Chair: Alberto Minuti
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
A design methodology for class-C oscillators implemented in ultra-scaled technologies is presented. Emphasis is set on the challenge of the minimization of the noise contribution of the bias circuitry, which is particularly relevant due to the increased flicker noise in ultra-scaled technologies. A case study oscillator, in a FinFET 16nm CMOS technology, exhibits a simulated phase noise as low as -116.7 dBc/Hz at 1MHz offset from the 13.2 GHz carrier, while drawing 10.3mA from the 0.95V supply. The simulated tuning range is 44%.
A 20-GHz Multi-Core Digitally Controlled Oscillator with -118 dBc/Hz Phase Noise at 1MHz Offset in 28nm CMOS
This paper introduces a 20 GHz multi-core digitally controlled oscillator (DCO) designed for high-speed and high-precision radar applications. The multi-core architecture provides superior output power, lower phase noise, and better stability compared to a single-core oscillator. Fabricated using a 28nm CMOS process, the oscillator comprises four identical cores and exhibits excellent phase noise performance, with a value of -118 dBc/Hz at 1 MHz offset from 19.5 GHz, 18% tuning range and -189.6 Figure of Merit (FoM).
A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2V Supply
This work presents wide-band/wide range Variable Gain Amplifier (VGA) based on the Quantized-Analog (QA) processing. The VGA is formed by an array of sub-units that amplify different portions of the input signal. The gain variation is obtained by acting on the signal correlation among adjacent slices that are eventually recombined on an output load. The VGA has been characterized, by inserting the VGA inside an optical RF front-end which includes a TIA stage and output buffer. Designed and layouted in 28nm CMOS, the VGA shows a gain variation of about 22 dB obtained in one stage, and a -3dB bandwidth of 29 GHz. At maximum gain, the average equivalent input-referred current noise is equal to 10.3 pA/√Hz while the Total Harmonic Distortion (THD) is below 2.3% for a maximum output swing of 500-mV peak-to-peak differential. The VGA consumes 64 mW while the complete front-end 124 mW from a 1.2V voltage supply
A 28 GHz and 38 GHz Dual-Band Up-Conversion Mixer for 5G Applications in 22 nm FD-SOI CMOS
This paper investigates a dual-band direct up-conversion mixer operating at 5G millimeter-wave (mmW) bands. To prove the concept, the mixer is implemented in a 22nm FD-SOI technology. A Gilbert cell was applied for the mixer core to achieve a high local oscillator signal (LO) suppression. An active balun was integrated on-chip to manage and optimize the LO phase- and magnitude-mismatch. Dual-band and broadband matching networks enable dual-band operation. The mixer has a total power consumption of 38mW including the LO active balun, mixer core and RF output buffer. The measurements show a conversion gain of −1.2 dB and 0.7 dB and a 1-dB output compression point (oP1dB) of −2.5 dB and −0.6 dB at 28GHz and 38GHz bands, respectively. The core area of the design is 0.24mm2. The mixer compares well against other designs operating at 5G mmW bands by showing one of the highest oP1dB, a comparable conversion gain and power consumption. To the best knowledge of the authors, this is the first 5G dual-band up-conversion mixer from technology node 22nm and below.
A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO
A differential delay cell without a cross-coupled latch is proposed for a two-stage ring voltage-controlled oscillator (RVCO). In the proposed delay cell (PDC), an RC network is used in place of a cross-coupled latch to exhibit a negative conductance. It reduces the power consumption in the RVCO significantly. Two paths from the output node for discharging current are added in the PDC. It reduces the discharging time of the output node which enhances the operating frequency by almost 50%. The PDC utilizes an RC network to reduce the peak-to-peak jitter of the RVCO by making the noise current sharp, similar to an impulse function. This design approach effectively minimizes the root mean square (RMS) value of the impulse sensitivity function, resulting in stable output with reduced jitter. The post-layout simulations are performed in 65nm CMOS technology using 1V supply voltage. At a frequency of 1.6 GHz, the proposed-RVCO (PDC-RVCO) shows excellent performance with a phase noise of -100.4 dBc/Hz at an offset frequency of 1 MHz. The power dissipation in the PDC-RVCO is reduced by 86.4% as compared to conventional RVCO. The peak-to-peak jitter is improved significantly by 29.7% and the figure of merit (FOM) is improved by 11 dB in the PDC-RVCO than conventional RVCO with a minor increment in area. The PDCRVCO has the lowest (FOM)(the lower, the better) compared to other RVCO architectures in the literature.
|11:20-13:00||B3 | Data Converters I |
Chair: Salvatore Pennisi
A Skew-Insensitive Switched Source-Follower Analog Frontend for Time-Interleaved ADCs
This paper presents a two-stage switched source-follower analog frontend (AFE) with high dynamic performance, by ingeniously combining the input-buffer and the track-and-hold circuits. The proposed placement of the switches facilitates the circuit’s realization in advanced CMOS technologies, and it makes the circuit equally insensitive to any signal-dependent charge-injection. Moreover, a single nMOS switch can be efficiently shared among time-interleaved (TI) AFE channels in any traditional TIADC architecture. This way, the proposed two-stage AFE circuit becomes skew-insensitive. Operating at 2 GS/s, the AFE achieves a simulated peak spurious-free-dynamic-range (SFDR) of 76 dB for a 996 MHz input signal with a 700 mVPP amplitude. Implemented in a 28 nm bulk CMOS process, it consumes 17 mA from a nominal analog 1.8 V power supply. Last but not the least, the proposed two-stage AFE circuit enables the combination of thick-gate and thin-gate devices avoiding any kind of reliability issues.
Homogeneity Enforced Calibration for Pipelined ADCs Including Nonlinear Stage Amplifiers
High-speed pipelined analog-to-digital converters (ADCs) are central components in many signal processing systems. Besides a high sampling rate, linearity is a key performance criterion for ADCs. The ADC's linearity can be drastically increased with calibration techniques, which are heavily investigated. On this matter, the homogeneity enforced calibration (HEC) approach was recently introduced, covering gain and digital-to-analog converter (DAC) mismatches of a pipelined ADC. The HEC approach enables short calibration times, and high calibration performance without the need for a precisely known test signal. In this work, we improve the HEC approach such that nonlinear stage amplifiers are calibrated besides gain and DAC mismatches. The calibration performance of the improved HEC approach is verified with behavioral simulations and shows a high spurious-free dynamic range (SFDR) improvement of 42.7 dB and a low remaining integral nonlinearity (INL).
A flexible column parallel successive-approximation ADC for hybrid neuromorphic computing
This work presents a concept and components for a Nyquist dual mode charge-redistribution SAR ADC in a 65 nm-process. Its fast mode (62.5 MS s−1 ) offers 7 bit resolution using an interleaving technique and its precise mode 8 bit resolution at 12.5 MS s−1 . The ADC is specialized on the requirements of a parallel interface between analog and digital computing blocks in the neuromorphic BrainScaleS-2 (BSS-2) system. Furthermore, it offers a small area footprint of around 1500 µm2 and low power consumption. It targets at two main applications: A fast result readout for analog vector-matrix-multiplications as well as membrane potentials and other plasticity related observable in spiking neural networks (SNNs).
MMSE Estimator for Linearized Analysis and SNR of ADCs Tested with Sinusoidal Inputs
The classical formula for the signal-to-noise ratio (SNR) of an analog-to-digital converter (ADC), SNR=6.02N+1.76dB, is derived by assuming a full-scale sinusoidal input that is uncorrelated with the quantization error (QE) arising from the N-bit ADC quantizer. This premise is inaccurate, particularly for the ADCs backed off to have a limited number of bits, N = 1, 2,... , 5. This paper uses the minimum mean square error (MMSE) estimator to perform a linearized analysis for a generic N-bit ADC, which takes into account the interaction between the ADC quantization characteristic and the probability distribution of the sinusoidal input. The estimated linearized gain guarantees the uncorrelation between the input and the QE. We compare the derived SNR with the classical formula to demonstrate their differences.
Trade-Offs in Active and Passive NS-SAR ADCs Architectures for Ultra-Low Power Audio Activity Detection Applications
This paper reports an architectural comparison between active and passive solutions for audio band Noise-Shaping Successive Approximation Register Analog-to-Digital Converters (NS-SAR ADC). The goal is to illustrate the advantages and drawbacks of these architectures when dealing with Ultra-Low Power (ULP) circuits that demand also the smallest possible area and a good technology scalability, like Audio Activity Detection (AAD) for MEMS microphones chains.
|11:20-12:40||C3 | VLSI and SoC Applications |
Chair: Yoko Uwate
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor
Reconfigurable processors are hardware architecture that allows for the dynamic configuration of processing resources to optimize performance and power consumption, using the partial reconfiguration technique to modify a portion of the design or update it without affecting the entire system. In this work, we present an automatic reconfiguration technique that leverages machine learning algorithms to automatically select the optimal configuration of a general-purpose hardware accelerator according to the workload executed run-time, formulating the problem as a Contextual Bandit (CB) case with the Linear Upper Confidence Bound (LinearUCB) algorithms using the RISC-V Klessydra family cores as a case of study.
CFPM: Run-time Configurable Floating-Point Multiplier
Approximate computing is a new approach that can help to reduce the power consumption in error resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper we introduce an adjustable floating-point multiplier in which groups of partial products can by dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjust at run-time based on the users’ requirements. The developed circuits are synthetized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art show good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.
Enhanced Soft GPU Architecture for FPGAs
Nowadays, General Purpose computing on Graphic Processing Unit (GPGPU) is deeply exploited in many application fields due to its high versatility and energy efficiency. Over the past decade, different solutions have been proposed to implement an embedded (soft) Graphic Processing Unit (GPU) on top of a Field Programmable Gate Array (FPGA) for GPGPU purposes, combining the performance and ease of programming of GPU architectures with the flexibility and reconfigurability of FPGA platforms. This paper describes the process of improving the hardware architecture of the soft GPU utilized in ICU4SAT project: an embedded GPU core built for FPGA platforms that is configurable, scalable, portable, and designed specifically for GPGPU purposes. Our improvements increase the compatibility of the soft GPU with the OpenCL standard through two major upgrades: 1) the addition of a local memory space in the memory hierarchy and 2) the addition of a barrier mechanism between the various threads. Each new feature is accompanied by an extension of the Instruction Set Architecture (ISA). The new features trade a relatively small increase in resource utilization for enhanced functionality without affecting the critical path.
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip
For many years, General Purpose Computing on Graphic Processing Units has been widely exploited in different fields of application. The hardware architectures enabling this kind of computation are increasingly complex, and their use for on-the-edge applications is often constrained by the limited resources that characterise the systems involved. As such, implementing Graphic Processing Units as soft architectures on Field Programmable Gate Arrays could permit to tune their size, performance and resource usage accordingly to the application requirements. Exploiting the so-called Dynamic Partial Reconfiguration technology can allow specialisation of part of the system architecture, creating heterogeneous computing systems with better resource utilisation and lower power consumption. In this work, we describe the implementation on Field Programmable Gate Arrays of a System-on-Chip featuring a soft-Graphic Processing Unit, whose size and performance have been tuned by means of Partial Reconfiguration. Considering the Sobel Filter as a reference kernel, we discuss some results for reconfiguration time and throughput. Furthermore, we identify the minimum task sizes for which initiating the reconfiguration process gives an advantage in terms of execution time.
|15:00-17:00||A4 | Power Circuits I |
Chair: Alberto Gola
A Fast-Response Resonant GaN Converter with Post-Regulation for Distributed DC-Grid Feed-In
A converter for distributed feed-in from a small LV bus to a HV DC-grid is presented. The converter system is comprised of a resonant LLC stage, boosting the input voltage with up to 2.5 MHz switching frequency and a post-regulating high-efficiency buck converter. The input LV-bus is designed to operate at 30 V and is interfaced to a 350 V grid. The converter regulates the LV-bus using cascaded control of the current mode post-regulator, enabling fast input power steps and reduced bus capacitance. The converter features a 99 % efficient buck-converter with a peak system efficiency of 95 %.
A Fast-Response Reference Current Source for High- and Low-Side High-Voltage Current Mirrors for Gate-Shaping Digital Gate Drivers
This paper presents the design of a fast-response reference current (IFRR) source being the reference for the high-voltage output current sources of a gate shaping digital gate driver for Silicon-Carbide power MOSFETs. By shaping the switching waveform driving the power MOSFET, there are significant improvements regarding energy efficiency and electromagnetic compatibility obtainable. The maximum reference current for the output current mirrors of the gate driver is 44mA with a total output current of 5.6A. A maximum startup time of less than 50 ns over process and mismatch variations and the full temperature range of -40C to 150C is achieved. The total current consumption is 4:12mA from 5V with a reference current of 44.7mA from 20V while operating. The turn-off current consumption is 0mA from 20V and the standby current consumption is 9.27mA respectively.
Integrated GaN digital soft start-up for switching power converters
This paper presents an integrated soft start-up circuit implemented in a 0.5-µm GaN on Si technology suitable for on-chip integration in power applications. The proposed approach avoids the use of large on-chip or external capacitors to overcome the problem of voltage overshoot and inrush current at start up in switching power converters. It could be also adapted to the specific application by choosing the number of Flip Flops, or, for large start-up periods, using a counter, and setting the desired start-up signal duty cycle. Moreover, an optimized Flip Flop circuit topology has been proposed to reduce area occupation. The circuit working principle and the design challenges in GaN technology are discussed together with simulations. The circuit has been designed by considering worst-case conditions. A test buffer has been also included to drive the high external load capacitance of the readout device. Measured waveforms are reported that demonstrate the effective circuit operation and suitability for all-GaN integration.
Enhancement-mode p-GaN Comparators for power applications
This paper presents the design and comparison of three new comparators circuits for power applications using Enhancement-mode p-GaN HEMT Process Design Kit (PDK) developed by IMEC. The design challenge in this technology is the lack of P-type devices, therefore diode-connected structures with N-type devices are introduced as pull-up devices. Comparators are monolithicaly integrate with 200 V/10 A power p-GaN HEMT. The output voltage of the comparators is set to 6 V to turn-on the power device suitably. To verify the performance of the circuits, 1 MHz of input signal frequency is selected. Relevant parameters such as rising, falling and propagation delay times, together with the power-delay product are discussed. For rated output voltage and frequency, the lower rise/fall/propagation delay times achieved are 0.83/0.89/1.14 ns. Transistor-level simulations and proof of concept of each proposed structure are carried out through Cadence Software considering temperature and load variation.
Adaptive Constant On-Time Control Technique Application in Boost Converters
A continous-conduction mode synchronous boost converter controlled with adaptive Constant On-Time (COT) technique is presented. This method focuses on operating a DC-DC converter with a fixed switching frequency while retaining the benefits of a COT, such as the elimination of the need for slope compensation. The complete topology will be briefly described, with special emphasis on the block that generates the converter on-time. Furthermore, the stability analysis of the system is examined. Simulation results are given at different output voltages, in order to show the versatility of the control loop in maintaining the frequency fixed by adjusting the on-time based on the operating point of the converter.
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions
A time-based compensator represents an effective solution to overcome the limitations of the traditional voltage mode controllers, as it allows to reduce both the die area occupation and the quiescent power consumption without compromising the control loop performances. Buck converters driven by high switching frequencies suffer from relatively low efficiency in medium/light load conditions, given the large power losses associated to the switching activity. Usually, to overcome this limitation the converter is operated in pulse frequency modulation (PFM), which makes it necessary to design an additional control loop and adds a DC offset to the output voltage as well. This paper proposes a variable switching frequency time-based control, able to operate the converter both in continuous and discontinuous current mode to guarantee high efficiency for a wide load current range. In addition, seamless frequency transition are obtained with a dedicated on-time correction circuit, which keeps the average inductor current constant upon variations of the operating regime. The proposed method boosts the efficiency in medium-light load conditions, ensuring an overall efficiency above 85% over a wide load current range. The effectiveness of this technique is supported by theoretical analysis and simulation results.
|15:00-17:00||B4 | Hardware Security |
Chair: Waleed Khalil
Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives
Once powerful enough quantum computers become feasible, many of the regularly used cryptosystems will be completely useless. Thus, designing quantum-safe cryptosystems to replace current algorithms is more crucial than ever. This paper presents the hardware implementation of one of the fundamental building blocks of all post-quantum cryptographic (PQC) algorithms, which are PQC-primitives, having NIST-PQCfinalists CRYSTALS-Kyber algorithm as a target. This work analyzes Keccak sponge function and the four SHA-3 algorithms used in CRYSTALS-Kyber, realizing the correct processing and handling of input information and integrating the four standards into one implementation for Kyber-III level of security. The synthesis results are provided for 65-nm technology, while Artix-7 XC7A75-3 is chosen as the implementation platform. The efficiency and the performance of the proposed architecture are compared in terms of area, frequency, clock cycles, and efficiency with the state-of-the-art.
Blockchain-based implementation of Tradable Green Certificates
Blockchain networks, given that they are not based on power-hungry proof-of-work methods, can be used in smart grid applications, in particular in the tradable green certificates use case. Thanks to the Blockchain and the smart contracts implemented, certificates can be tracked and exchanged between entities without the intervention of third parties, as well as keeping an immutable and reliable record of these certificates. This work proposes a hardware implementation of a green certificate trading system based on Blockchain, in which prosumers use hardware secure elements to implement the cryptographic tools used to interact with the Blockchain. Smart contracts help to automate these processes, deleting intermediaries, saving costs and avoiding bureaucracy.
Correlation Electromagnetic Analysis on an FPGA Implementation of CRYSTALS-Kyber
Post-quantum cryptography represents a category of cryptosystems resistant to quantum algorithms. Such schemes are under the scrutiny of their mathematical security in the context of the NIST standardization process, but they are not side-channel secure at the algorithm level. That is why their side-channel vulnerabilities must be assessed by the research community. In this paper, we present a non-profiled correlation electromagnetic analysis against an FPGA implementation of the standard key-encapsulation mechanism, CRYSTALS-Kyber. The attack correlates an electromagnetic radiation model of the polynomial multiplication execution with the captured traces. With 166,620 traces, this attack correctly recovers 100% of the subkeys. Furthermore, a countermeasure is presented for securing the target implementation against the presented attack.
Low-complexity Machine Learning Architecture for Hardware-aware True Random Number Generators Assessment and Continuous Monitoring
A new machine learning approach of assessment and monitoring of True Random Number Generators (TRNGs) is explored in order to create a new technical framework for entropy source development and validation, based on the direct estimation of the core source entropy, which is suitable for hardware-based lightweight cryptography. It consists of the integration between a pre-processing stage and an Artificial Neural Network (ANN). The pre-processing stage continuously generates stochastically patterned images from number sequences provided by TRNGs with assigned entropy thresholds. The ANN processes the images to determine whether the TRNG entropy remains higher than the assigned threshold, dynamically, during the sequence generation. A custom dataset, generated from a Markovian TRNG has been used to train, validate and test a very compact 3-layer ANN. The model achieves accuracy, precision, recall, and F-score all equal to 98.28% averaged on the test set. The low computational complexity of the ANN, favored by the effectiveness of the pre-processing stage, which, in turn, requires a simple architecture to be implemented, proves that the proposed solution can be effectively employed for a perspective resourceconstrained hardware implementation.
Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrisically Robust PVT TRNG
In this paper we present a dynamic entropy generator based on the oscillator jitter, which uses a self- biasing technique to minimize process, voltage, and temperature (PVT) variations. The proposed circuit has the advantage of its intrinsic robustness due to self-biasing design, which eliminates the need of additional calibration steps and simplifies the circuit topology, with a negligible impact in area and power consumption. A frequency deviation below 15 % and a maximum jitter difference of 32 % under PVT variations, is obtained, in a 28 nm CMOS technology circuit prototype. For validation of the proposed circuit technique the IC prototype is compared with a standard ring oscillator and with traditional calibration techniques.
Design Space Exploration of TRNG Latches for Improved Entropy and Efficiency
True Random Number Generators (TRNGs) are a key building block in cryptography. In order to obtain random outputs, the TRNG must produce sufficient noise such that the probability of overcoming any offsets caused by on-die variations between devices, which are inescapable in CMOS processes, is high. In this paper, we analyze the metastable latch based TRNG design with regards to relative device strength, type, and size to determine the tradeoffs in robustness to offsets, bit-rate, and power.
|15:00-17:00||C4 | Modeling, Optimization and Characterization |
Chair: Andrei Vladimirescu
A DC SPICE Level 3 Model for 4H-SiC lateral NMOSFET under strong inversion conditions
A DC SPICE model of a 4H-Silicon Carbide lateral n-type Metal Oxide Semiconductor Field Effect Transistors is proposed. Basing on a SPICE MOSFET Level 3 model, we introduce a novel equation of the threshold voltage, because its classic description is invalid due to the high density of traps at the oxide/semiconductor interface. Moreover, we also consider the body effects on the threshold voltage and on the channel mobility as well as the high-field effects. The accuracy of our model has been verified through the comparisons with experimental data and the relative Verilog-A BSIM4SiC model. The devices are fabricated with the 2μm CMOS process by Fraunhofer IISB and have channel length and width of 10 μm. The output and trans-characteristics are for room temperature and under different bias conditions of the drain, gate and body terminals.
Characterization of an integrated High-Voltage capacitance in Silicon-On-Insulator technology
In recent years, the topic of motor inverterization has become increasingly popular as it offers numerous benefits in terms of energy efficiency and control. Central to this topic is the development of gate drivers, which are critical components in controlling the switching of power devices in the inverter-leg. The introduction of high voltage integrated circuits (HVICs) has greatly simplified the inverter system, but has also brought in new challenges in terms of communication between different voltage domains, each one of them isolated from each other up to several hundreds volts. In this paper, the characterization of an integrated high voltage capacitance in silicon-on-insulator (SOI) technology placed between two voltage domains is presented, allowing for a bilateral form of communication at the cost of withstanding high voltage at its terminals. The measurement of this element required a dedicated circuital structure, and the value of the capacitance was measured to be around 127 fF and its breakdown voltage at around 1800 V.
Noise Analysis in Voltage Mode Controlled DC-DC Converters
This paper presents a strategy for performing noise analyses in a boost converter with Voltage Mode Control (VMC). The proposed analysis is particularly powerful when each of the power regulator transfer functions is known. The approach is demonstrated by injecting a noise source, treated as a single sinusoidal tone, in two scenarios: within and beyond the first Nyquist band. The effectiveness of the model is verified by comparing the calculated gains through FFT (Fast Fourier Transform) of the output voltage with the ones computed from AC analysis.
A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC
Resistive random-access memories (RRAM) suffer from process variabilities. To mature the fabrication process, it is essential to evaluate the critical operating conditions precisely. This work proposes an integrated system for characterizing on-chip RRAMs. The proposed system consists of two major parts: Accessing circuits that allow programming RRAM with external references and a flexible readout circuit using a calibratable integrating analog-to-digital converter (ADC). The design allows a flexible selection of the readout voltage from 0 to 500mV and the readout time from 0.12 us to 510 us by adjusting the system’s clock frequency and output precision. The simulation shows a readout error less than 0.5 LSB for maximal input using offset calibration. The proposed system is designed using IHP 130nm Technology.
Self-Adaptation of Line Driver Pre-Emphasis Parameters via Embedded Line Loss Sensing
The paper proposes a method for automated optimization of line driver pre-emphasis parameters by utilizing the measured transfer function (TF) of the channel. For this purpose, pulse-echo measurements are performed in which pulses with a given frequency and duration are transmitted into the channel and the amplitude of the resulting echo detected to evaluate frequency-dependent line loss. To avoid the need for a power-hungry high-speed ADC, the echo amplitude is indirectly detected using transmit pulses with different amplitudes and a simple comparator-based circuit that detects when the echo amplitude exceeds a user-defined threshold. The result is used to estimate the cable loss, and the process repeated for different input frequencies to estimate the channel TF. The proposed estimation procedure is validated using a transistor-level implementation in 65nm CMOS for data rates up to 1Gb/s, channel losses up to 15dB, and a receiver reflection coefficient of -20dB.
Variability-aware electrochemical metallization based memristive neural network for pattern classification
In recent years, memristive neuromorphic systems have gained significant attention. In our previous work, we developed a physics-based framework to model transport in electrochemical metallization (ECM)-based memristors with layered materials as switching layers, which was implemented in Verilog-A. In this work, we demonstrate the efficacy of this model in a crossbar array/neural network for pattern classification and analysis of its performance. The performance of the system is analyzed based on classification accuracy in ideal and non-ideal conditions. We anticipate that this will provide valuable insights into the design of these systems before the actual fabrication.
|Wednesday, June 21st|
|10:50-12:30||A5 | Data Converters II |
Chair: Antonio Aprile
A Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
This paper describes a calibration method for a 2-1 MASH Σ∆M using passive integrators. Due to process variations the RC product can vary, causing a degradation in circuit performance. Therefore, a circuit measuring the RC time constant and converting it into a digital coefficient, was designed. This coefficient is used to calibrate the reference voltage of the Σ∆M to decrease the variability of the feedback signal and to calibrate the digital cancellation logic (DCL), improving quantization noise cancellation. Electrical transient noise simulations results of the Σ∆M with calibration prove validity of the presented method showing performance improvement in worst corners.
Ultra-Low Power Heart Rate Estimation with VCO-based ADCs
A system and circuit approach to perform ultralow power heart estimation is proposed towards biomedical wearables. A voltage controlled oscillator based analog-to-digital converter (VCO-based ADC) implemented with a ring oscillator is used for the digitization of a blood volume pulse (BVP) signal. The digital output data then feed digital logic circuits that perform very simple operation to achieve a very accurate measurement of the heart rate. The resulting circuit is mostly scalable, consumes nWs and the accuracy performance is completely independent from the VCO non linearity. A proposal has been designed using a 65 nm CMOS node leading to a power consumption of only 108 nW and errors less than 1 bpm.
A Power-Efficient Successive Approximation Algorithm for Low-Activity Signals
This paper presents a new successive approximation algorithm that can digitize the second-order difference of signal samples rather than each sample point individually or plain difference of sample points. This method is able to drastically reduce the number of comparisons required to convert a new signal sample to digital numbers, from a fixed N comparisons commonly used in a conventional successive-approximation-register (SAR) analog-to-digital converter (ADC), to a number in between 2 and N for almost all the signal samples in an N-bit ADC. This proposed algorithm is implemented in MATLAB and tested on electrocardiogram (ECG) signals in this work. The experimental results show that our algorithm can reduce the number of comparisons by 58.75% compared to the conventional SAR ADC, and by 17.78% or more compared to several other state-of-the-art methods. In addition, it is able to reduce the DAC updating time by the same percentages, leading to lower power consumption in both DAC and digital parts of SAR ADC.
A 880nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm
This paper presents a digital intensive, compact and energy efficient 13-bit, 100-kS/s Differential Relaxation Digital to Analog converter (Diff-ReDAC) in 180nm CMOS. The Diff-ReDAC is able to operate in a supply voltage range from 0.45V to 1V having power consumption ranging from 420nW to 2,650nW. It has an area footprint of only 7,800um2 while achieving, at 0.6V a maximum INL (DNL) of 1.07 LSB (0.96 LSB) , 77.81 dB(77.52 dB) of SFDR (THD) and 65.82 dB SINAD, resulting in 10.64 ENOB. Its low power dissipation of 880nW results in extremely competitive energy efficiency (area-normalzed energy efficiency) figures of merits FOM (FOMA) of 172 dB (178 dB).
A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators
This paper proposes the design of a Pulse Width Modulation Digital to Analog Converter (PWM-DAC) for Analog in-Memory Computing. The converter generates voltage pulses, with pulse-width proportional to the 7-bit digital input, in sign-magnitude format. The circuit is designed in a 22-nm FDSOI technology, with a layout tailored for the severe pitch and area requirements of the memory array for AiMC. The circuit achieves sub-500 fJ/conversion energy consumption, supplied at 0.85 V. The converter obtains an Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL), normalized at the LSB, lower than 7% and 12%, respectively.
|10:50-12:30||B5 | Image and Data Processing |
Chair: Eric Gutierrez
ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information
Fault resilience in computer vision algorithms is paramount in critical applications such as autonomous driving or surveillance. Convolutional neural networks (CNNs) are usually used in these tasks to identify objects of interest, which are passed to other decisional algorithms and used to take specific actions. However, incorrect detections due to computation errors could pose a safety risk. In this work, we present ERODE (Error Resilient Object DetEction), a framework that can be paired with a CNN to filter the detections by identifying possible errors and restoring the correct predictions, improving the fault-resilience of the system. The proposed framework leverages the temporal correlation among consecutive images and CNN outputs, using motion estimation and tracking techniques to infer whether computation errors have occurred and, in that case, produce a new set of outputs. In order to evaluate the performance, precision and recall of the CNN with and without ERODE support have been computed and compared using the MOT17DET dataset, and EfficientDet D0 quantized to 16-bit, with errors injected in the activations computed during the inference. The experimental results show significantly reduced task accuracy degradation induced by bit-flips, proving that ERODE can increase the system’s fault resilience.
A hardware-aware neural architecture search algorithm targeting low-end microcontrollers
Hardware-aware neural architecture search (HW NAS), the process of automating the design of neural architectures taking into consideration hardware constraints, has already outperformed the best human designs on many tasks. However, it is known to be highly demanding in terms of hardware, thus limiting access to non-habitual neural network users. Fostering its adoption for the next-generation IoT and wearable devices design, we propose an HW NAS that can be run on laptops, even if not mounting a GPU. The proposed technique, designed to have both a low search cost and resource usage, produces tiny convolutional neural networks (CNNs) targeting low-end microcontrollers. It achieves state-of-the-art results in the human-recognition tasks, on the Visual Wake Word dataset a standard TinyML benchmark, in just 3:37:0 hours on a laptop mounting an 11th Gen Intel(R) Core(TM) i7-11370H CPU @ 3.30GHz equipped with 16 GB of RAM and 512 GB of SSD, without using a GPU.
Assessment of Recurrent Spiking Neural Networks on Neuromorphic Accelerators for Naturalistic Texture Classification
This paper presents the implementation of a Recurrent Spiking Neural Network (RSNN) using surrogate gradient descent for naturalistic textures classification. The implementation choices for the RSNN are limited to hardware-friendly models since it is intended to be integrated into an electronic skin system. Hence, a comparison between the von-Neumman and neuromorphic computing approaches has been assessed in terms of hardware efficiency. The energy consumption per inference of the proposed model is estimated using the KerasSpiking tool built-in NengoDL framework, on three different devices namely: GPU, Intel Loihi, and SpiNNaker. The obtained results indicate that the aforementioned neuromorphic devices achieve several orders of magnitude gains in energy over von-Neumman hardware. Moreover, the proposed RSNN model overcomes similar state-of-the-art solutions in terms of classification accuracy and hardware complexity making it a promising candidate for embedded electronic skin applications.
Modular 76-channel instrument for Broadband Raman Spectroscopy
Raman microscopy is a label-free and non-invasive technique to reveal the chemical compounds of a sample. However, standard Raman microscopes acquire a single frequency at a time, preventing fast imaging as many biological applications require. Here, we present the preliminary development of a multichannel CMOS-based readout for the simultaneous acquisition of 76 frequencies of the Raman spectrum using the broadband stimulated Raman scattering technique. The acquisition system employs the lock-in technique and a custom multichannel CMOS chip to enable a low-noise operation and a parallel architecture for fast imaging. An FPGA-based Digital Signal Processing chain reduces the low-frequency noise by exploiting a 2-step demodulation technique. The hardware design of the system based on a motherboard and several module PCBs to realize a highly space-optimized architecture is also presented. Particular emphasis is placed on the experimental results obtained with the 2-step demodulation technique by means of bench tests.
Digital One-Shot Charge-Balancing Method for Implantable Current-Mode Electrical Stimulation
A low-power digital charge balancing system, which ensures the safe operation of constant-current biphasic stimulations is presented. The concept of the proposed charge-balancing technique is to utilize a hybrid method consisting of anodic pulse modulating and short-term offset current injection. Furthermore, a dual thresholding strategy is considered to guarantee precise and low-power imbalance compensation. The charge-balancing system is capable of canceling large persistent imbalances by adjusting the input code of an 8-bit current-steering digital-to-analog converter (DAC) as well as injecting an offset current in a power-efficient way. The performance of the designed charge balancer is evaluated by modeling a 1 mA biphasic constant-current stimulator with 8-bit DAC resolution. The charge-balancing system is implemented on a Cyclone IV FPGA, and measurement results evidence the safe, accurate and low-power charge-balancing performance in which the balance offset current injection is performed in less than 5% of the stimulation time while the dynamic power consumption is at 0.76 mW.
|10:50-12:30||C5 | Sensing and Driving Circuits |
Chair: Elisabetta Moisello
Comparison of Interface Circuits for Continuous-Time Read-Out from MEMS Microphones
This paper presents a brief review of continuous-time, low-power integrated CMOS analog front-ends (AFEs) for capacitive transducers, such as MEMS microphones. Source follower (SF), common source (CS), differential amplifier (DA) and differential difference amplifier (DDA) are compared in terms of input-referred noise, current consumption and acoustic overload point. All interface circuits have been theoretically analyzed, designed, and simulated. The SF structure turns out to be the best solution in all aspects. The main limiting factor for the noise performance turns out to be the flicker noise component.
9.9 V High-Voltage Switch in a standard 180 nm CMOS technology for MEMS Inclinometers
In this paper a high-voltage switch, capable of delivering a voltage of 9.9 V to a MEMS actuator is presented. This circuit is implemented in a standard 180 nm CMOS technology with a nominal voltage of 3.3 V for the I/O transistors. The switch is implemented following the stacked transistors principle, to ensure that none of the devices is stressed beyond the acceptable limits. Moreover, all the additional circuitry such as the pre-driver and the voltage buffers to generate intermediate voltage levels are also presented in detail. Compared to other designs shown in the literature, the implementation presented here enables the largest variation of the output range, from 5 V to 9.9 V. Post-layout simulation results validate the successful operation of the proposed architecture
A pilot study: electronic skin sensitive to the grasping speed
Robotic grippers aim to be increasingly precise, being effective in object manipulation and gentle on fragile objects. In this scenario, endowing a gripper with a distributed sensing system sensitive to a set of dynamic touch patterns seems crucial to improve the gripper as a manipulation device. In humans, the velocity of touch influences haptic perception with impact on object manipulation and exploration. Therefore, the current study has also potential to drive sensory feedback for intuitive human-in-the-loop control of haptic devices. In this study, we embed an electronic skin (e-skin) into the thumb fingertip of a robotic gripper to investigate tactile sensor response during an easy task of object grasp-release, thus focusing on normal forces only. The reference electronic skin is a tactile sensing system based on piezoelectric polymers, coupled to a rigid substrate and covered by an elastomer layer. The cover layer has been chosen because it is easily disposable and for its ‘human skin’-like softness characteristics. Main scope is to investigate whether piezoelectric sensors are sensitive to the grasping speed. The parameter we set is the speed of the servomotors for the proximal and distal flexion of the fingers. Increasing the speed of the servomotors results in an increase of the speed of the phalanges, i.e. the grasping speed. Two objects of different stiffness have been tested and three different features of the sensor signal have been analyzed. These preliminary results show an increasing linear behavior of the amplitudes of the maximum and minimum peaks in the sensor signal with the servomotor speed. The size of the processing window seems not to impact the relation between the signal energy and the speed, thus suggesting that the smallest window could be effectively used to extract such feature in embedded devices in real-time. These pilot studies are hints at the fact that coupling information from such features could enable inferring the grasping force and speed.
A C/V Converter for MEMS Gyroscope Readouts Featuring a Single Stage Class AB OTA
In this paper, we present a fully differential single stage charge-to-voltage (C/V) converter with a class AB output stage for gyroscope readout circuits. The proposed amplifier offers low noise and low power consumption by using a current reuse architecture in the OTA core while also providing a rail-to- rail output swing for a good signal-to-noise ratio (SNR). In this work we benefit from a single stage amplifier which has the advantage of requiring no compensation capacitance, therefore, reducing the overall area. Moreover, having a class AB output stage allows us to reduce the needed quiescent current compared to a class A output stage while offering a high voltage swing at the output. In order to ensure that the proposed amplifier fulfills the sensor frontends specifications, extensive simulations have been carried out over a temperature range from (−5°C to 70°C) including process, voltage and micro electro-mechanical system (MEMS) variations. The simulated power consumption is below 37 μW from a 1.6V supply and the input-referred noise stays below 35nV/√Hz from 35kHz to 10MHz. The C/V is designed in a 40nm CMOS process and offers a gain drift of 0.4% from −5°C to 70°C, a phase drift of below 3.5 mrad and a total harmonic distortion (THD) of below 1.5% for an output swing of 1.2Vpp over all process corners while consuming an area of 145 x 165 μm².
A Reconfigurable Dual-Mode Integrated CMOS Laser Diode Driver for iToF/dToF Based 3D Sensing
A reconfigurable dual-mode laser diode driver has been designed in a standard 180-nm CMOS process for iToF(indirect Time-of-Flight) and dToF (direct Time-of-Flight) based 3D sensing. A reconfigurable and power-efficient driver output stage is proposed, which enables both iToF and dToF operation. In iToF mode, the driver produces a maximum output current of 4.2 A with 50% duty cycle. A ringing suppression circuit is also introduced to reduce the undesired ringing at the end of each pulse. In dToF mode, the driver generates a 3.8-A peak pulse with a minimum pulse width of 737 ps. The output efficiency is 87% in iToF mode and 92% in dToF mode with 4-A output current. To the authors’ knowledge, this is the first reconfigurable dual-mode laser diode driver compatible with both iToF and dToF LiDAR systems.
|14:30-16:30||A6 | Analysis and Modeling of Radio Frequency Circuits |
Chair: Angelo Malvasi
Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs
Fractional-N digital phase-locked loops (DPLL’s) typically use a multi-stage noise-shaping (MASH) digital Delta-Sigma modulator (DDSM) divider controller to synthesize an output frequency that is a non-integer multiple of the reference. The quantization error (QE) arising from the divider controller, if not being canceled prior to reaching the time-to-digital converter (TDC), can overwhelm the TDC input jitter level and in turn deteriorate the phase noise (PN) of the TDC, and hence that of the DPLL at the system level. This sets a performance limit for such DPLLs, for which case it is crucial to predict explicitly the worst-case output PN in order to analyze fractional-N PN mitigation techniques critically. This paper investigates this scenario, for which the input jitter analysis and output PN prediction are performed. Multi-rate discrete-time behavioral simulation at the system level confirms the accuracy of our analytical predictions.
Noise Figure Analysis in Current Mode Direct Conversion Receivers
The purpose of this paper is to face the problem of the noise figure calculation in case of direct conversion current mode receiver (RX). In the considered receivers architecture the down-conversion operation is done by mixing the input current signal by a square waveform oscillating at a frequency equal to the carrier of the RF signal. Moreover, the presence of the harmonics in the square waveform mixing signal produces noise folding which worsen the noise figure of the RX. A possible solution has been proposed and it consists to introduce a bandpass filtering after the low-noise transconductance amplifier. After a system level analysis of the problem a circuit example in 65nm CMOS technology is proposed. Calculated and simulated results for the noise figure match very well demonstrating the correctness of the proposed approach.
A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem
Passive resistive mixers find applications in many modern RF and mm-wave circuits, from telecommunications to radar and automotive systems. This paper presents an equivalent Thevenin circuit for the analysis of the gain and bandwidth of the passive resistive mixer, that takes into account the source resistance and a finite off-resistance of the switches. This model is applied to practical use cases and validated against simulations.
Influence of Transistor Compact Model Accuracy on Phase Noise Simulation
When designing oscillatory circuits, intuition about phase noise is often hindered by the complex underlying mathematics and proprietary device compact models. While these models are very accurate, their complexity (and sometimes encryption) can lead to a black-box behavior. For the investigation of circuit topologies regarding noise it is desirable to work with more accessible, general compact models, decoupled from a specific technology node. We investigate how differences in compact model accuracy influence the simulation results of phase noise properties. For two exemplary circuits phase noise properties are calculated using a highly accurate foundry model and a simple SPICE level 1 model. Comparison shows that qualitatively correct results can be expected even for the simple compact model, especially when the susceptibility of oscillator phase as a function of time is investigated. However, simulations of statistical phase noise properties (e.g. the phase noise spectrum) are based on a fragile balance of positive and negative phase contributions, and are shown to vary more severely for different models.
Bi-directional Distributed Amplifier in 0.11 μm CMOS Technology
This paper presents and compares two different design approaches for bi-directional distributed amplifiers (BDDA) in 0.11 μm CMOS technology. Distributed amplifiers (DA) and BDDAs can be designed starting from T-type and π-type unit cells of artificial transmission lines (ATL). This paper specifically compares T-type and π-type BDDAs in terms of gain, bandwidth and chip area. Designing DAs and BDDAs with π-type unit cells provide advantages from two different perspectives. Firstly, π-type BDDAs can be designed with more gm-cells than T-type BDDAs with the same chip area. This provides higher gain without the cost of chip area because a π-type unit cell has one less inductor than a T-type unit cell. Secondly, smaller-sized gm-cells can be designed owing to extra active cells in π-type BDDAs in order to increase the bandwidth of BDDAs. Hence, π-type BDDA can provide higher bandwidth than T-type BDDA with the same chip area if desired. The simulated gains of BDDA with three T-type and four π-type unit cells are 8.5 dB and 10 dB at 2-19.5 GHz. In addition, BDDA built using π-type unit cells with active cells equivalent to four fully active gm-cells is designed with smaller gm-cells to achieve higher bandwidth. Thus, 8.5 dB gain is obtained over 2-23 GHz. The chip areas are almost the same as the BDDA with three T-type unit cells for all versions of designed π-type BDDAs.
Low-Loss Tunable-Phase Transmission Line Couplers - A Comparative Study
RF circuit implementation usually suffers from undesired phase shift of the input signal when operated over a wideband due to inherent behavior of sub-circuits. A transmission line based sub-degree phase tunable active coupler network is being proposed in this work. A compact low-loss transmission line whose phase can be adjusted depending on the bias applied to a common-source amplifier in the coupled path is presented in this paper. Two active couplers with the same transistor size, different insertion phase and sub-degree phase tunability are comparatively studied with previously known techniques. The simulations are carried out using 22FDSOI PDK from Global Foundries
|14:30-16:30||B6 | Power Circuits II |
Chair: Ashis Maity
An External-Capacitorless High-PSR Linear Voltage Regulator With Source-Follower-Based Pre-Filter
This paper presents an external-capacitorless linear voltage regulator for supply noise decoupling of a sensitive clock synthesizer circuit in a gate driver IC. The design generates a precise and low-noise 1.8V output voltage from the noisy 5V supply rail of the system. The regulator architecture is based on a source follower pre-filter in combination with an NMOS passtransistor. A worst-case PSR of 43dB is achieved across the whole load current range of up to 5mA. The total quiescent current is 20μA and the occupied area, including the 8pF on-chip output capacitance, is only 0.012mm2. The circuit is implemented in a 0.18μm BCD technology.
A Transient Response Improved Output Capacitorless LDO
In this paper, a transient response improved output capacitorless low dropout regulator is designed in standard 0.13 μm CMOS technology. A method based on adaptively sense network (ASN) to increase the slew rate and provide extra discharge loop is adopted, which suppresses the undershoot and overshoot of output voltage. Simulation results reveal that the output voltage undershoot and overshoot is 97.03 mV and 140.87 mV, when load current step from 10 μA to 30 mA with the edge time is 100 ns, respectively. And the output voltage recovery time is less than 0.35 μs, the fast settle time is also achieved. Besides, the linear regulation of load and supply voltage is 0.043 mV/mA and 1.467 mV/V.
A Fast-Transient mitigation technique for a dual-loop, linear search, self-timed, Asynchronous Digital LDO
In this paper is presented a fast-transient mitigation technique which applies to a self-timed, dual-loop Asynchronous Digital LDO. The number of conducting transistors is controlled by an Asynchronous Finite State Machine (AFSM) employing a linear-search algorithm that is able to operate without a clock oscillator. It relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage. The proposed mitigation technique has two components. One relies on using a secondary loop that has bigger transistors. The LDO reaches steady state faster than the main loop due to the higher adjustment steps. The other component controls the operating frequency by altering the REQ-ACK protocol in order to sample and update the output faster. The circuit was simulated and fabricated using Infineon’s proprietary 130nm BCD technology and was assembled in SSOP-14 plastic package. Also, the proposed circuit was measured and the results show more than 50% improvement and a settle time reduction with a factor of 4 on sudden load changes while a light increase in output voltage ripple for steady-state operation must be considered.
Common-Gate Zero Current Detector with Body-Voltage Based Offset Compensation
A zero-current-detector (ZCD) circuit is usually required in switching dc/dc converters to enable low current mode operations such as discontinuous-current-mode. The ZCD input offset arising from process variations and components mismatch makes the converter to switch with a non-zero inductor current, reducing the overall conversion efficiency. This paper presents a ZCD structure that ensures fast and accurate zero- crossing detection of the inductor current by checking the drain-source voltage of the low-side switch. The proposed offset correction technique acts on the body voltage of two NMOS of the comparator, sensing the output current of a differential pair during the first phase. In the comparison phase, the corrected body voltage value is stored in a holding capacitor, drastically lowering the ZCD input referred offset. The effectiveness of this technique has been proved with transistor-level simulation in a BCD technology with 180nm CMOS. The input referred offset of the same ZCD topology, implemented with and without the proposed correction method, has been reduced by about a factor of 30.
A Sub-100 mV AC/DC Converter with Impedance Matching for Magnetic Field Energy Harvesting
Energy harvesting from ambient sources can be used to supply low-power devices in remote areas or where it is costly to replace batteries. Other than light, temperature gradients, vibrations and radio frequency electromagnetic radiation, it is also possible to harness ambient energy from an alternating electric or magnetic field. Magnetic field energy harvesting (MFEH) is possible with inductors near AC current-carrying power lines. This paper presents a novel converter for boosting the low-voltage AC output of small magnetic field energy harvesters to power standard electronic circuits. The design in a 180 nm CMOS process is illustrated and efficiency and system level power measurements are performed to proof the concept.
Sub-modular MPPT for Decentralised Grid Feed-in Under Fast Changing Irradiation Applications
A system for decentralised grid feed-in of solar sub-modules is presented. The system makes use of monolithically integrated sub-modular maximum power point tracking, boosting the output voltage to 30 V. Multiple sub-modules of different topologies and insolation can thereby be combined to feed into one DC-DC converter, each in turn feeding into a 350 V HV DC grid. This allows for novel applications, such as noise barriers or facades, reducing losses associated to traffic or pollution induced partial shading. Measurements show increased power extraction throughout partial shading events. Energy gain is highly dependent on shading frequency, length and affected module area. Sub-modular peak throughput lies at 140 W, while grid feed-in is limited to 600 W per converter.
|14:30-15:50||C6 | Digital Circuits and Sub-Systems |
Chair: Javier Calpe
A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application
In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 24% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.
Improving Functional Coverage of Network-On-Chip Using Differential Evolution
Network-On-Chip (NoC) is a communication subsystem which has evolved as an alternative to bus-based System-On-Chip (SoC) architectures that simplify the physical implementation of the system. The functional verification of the NoC is a very important phase in the design life-cycle of a NoC-based SoC as it impacts the SoC’s behavior and latency. Automating the NoC functional verification process significantly reduce the time to market for such complex SoC designs. The use of differential evolution algorithm to create NoC traffic which obtains maximum functional coverage in less simulation time is one such method of automation.
Design and FPGA implementation of a high-speed transposed Farrow structure for arbitrary resampling in digital receivers
Sample rate conversion is a fundamental operation performed in the digital front-end of software-defined radio and all-digital receivers. Within this context, polynomial-based filters, such as the Farrow structure and its variants, are a sound solution when arbitrary resampling is required. This paper presents a design methodology and the results of the implementation on a field-programmable gate array (FPGA) device for a high-speed transposed Farrow structure based on a novel parallel architecture. The implemented architecture supported an input sample rate of up to 2.184 GHz with moderate utilization of the FPGA resources. Furthermore, signal-to-noise ratio and spurious-free dynamic range values higher than 87 dB and 98 dB were reported over a wide range of sample rate conversion factors. Our results may suggest an improvement in the trade-off between flexibility, complexity and thoughput compared with previous work in the field.
Design-Space Exploration of Mixed-precision DNN Accelerators based on Sum-Together Multipliers
Mixed-precision quantization (MPQ) is gaining momentum in academia and industry as a way to improve the trade-off between accuracy and latency of Deep Neural Networks (DNNs) in edge applications. MPQ requires dedicated hardware to support different bit-widths. One approach uses Precision-Scalable MAC units (PSMACs) based on multipliers operating in Sum-Together (ST) mode. These can be configured to compute N = 1, 2, 4 multiplications/dot-products in parallel with operands at 16/N bits. We contribute to the SoA in three directions: we compare for the first time the SoA ST multipliers architectures in performance, power and area; compared to previous work, we contribute to the portfolio of ST-based accelerators proposing three designs for the most common DNN algorithms: 2D-Convolution, Depth-wise Convolution and Fully-Connected; we show how these accelerators can be obtained with a High-Level Synthesis (HLS) flow. In particular, we perform a design-space exploration (DSE) in area, latency, power, varying many knobs, including PSMAC units parallelism, clock frequency and ST multipliers type. From the DSE on a 28-nm technology we observe that both at multiplier level and at accelerator level there is no one-fits-all solution for each possible scenario. Our findings allow accelerators' designers to choose, out of a rich variety, the best combination of ST multiplier and HLS knobs depending on the target, either high performance, low area, or low power.