|Monday, June 13th|
|09:15-10:30||A1 | RF Circuits and Systems I|
Chair: Piero Malcovati, University of Pavia, Italy
Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs
The divider controllers in fractional-N frequency synthesizers are typically digital ΔΣ modulators (DDSMs). The DDSM can contribute significantly on the phase noise and spur pattern in the output of a nonlinear synthesizer. A type of time-varying spurs and another type of fixed sub-fractional frequency spurs, denoted wandering spurs and horn spurs, respectively, have been observed in simulations and measurements of fractional-N frequency synthesizers with a MASH-based divider controller. Different families of DDSMs have been presented in the past which represent an alternative to MASH-DDSMs. Among those, the ENOP DDSMs are worthy of notice because of their performance in terms of nonlinearity-induced noise and spurs. In this work we show that ENOP-based divider controllers offer strong mitigation of both wandering and horn spurs.
Influence of Amplitude and Phase Imbalance on a Y-band Bootstrapped Frequency Doubler using 130-nm SiGe Technology
This paper presents a fully-differential bootstrapped Gilbert-cell-based frequency doubler designed in a 130-nm SiGe process to provide an output frequency of 220 GHz. At this frequency, an underlying asymmetrical layout of the switching quad leads to several problems such as output amplitude difference, phase difference deviating from 180°, and conversion gain (CG) degradation. An imbalance analysis is therefore carried out to understand the critical layout routings. The results show that the imbalance at the collectors of the transistors has the most severe impact on the differential output amplitudes and phases. On the other hand, imbalance at the base influences the CG mostly. Based on these findings, a frequency doubler was designed in the SiGe SG13G2 technology. The proposed frequency doubler achieves a maximum output power of -5.8 dBm and a 1-dB bandwidth of 25 GHz from 202.5 GHz to 227.5 GHz with 91 mW of dc power consumption in the full EM post layout simulation.
A Configurable Active Bandpass Filter with DC Offset Suppression for Direct Down-Conversion Wake-Up Receivers in 28nm
This paper presents the design of an integrated active band-pass filter for low-IF or direct down-conversion wake-up receivers suited for IEEE 802.11ba. Two gyrator-based second-order gm-C structures are used to achieve an overall low-pass filtering order of at least 4. Fully differential operational transconductance amplifiers (OTA) with capacitive source degeneration and capacitive load result in a band-pass frequency response. This way, the down-converted signal is filtered and DC offsets from previous stages are suppressed. By adding two programmable gain amplifiers (PGA) that show first-order low-pass behavior as well, the whole structure also acts as a gain stage and the filtering is slightly improved. The band-pass filters and PGAs are arranged in an alternating fashion in order to prevent possible DC offsets from propagating through the chain. Every stage features a common-mode feedback (CMFB) loop. The nominal filter bandwidth is from 150kHz to 2MHz and the upper band edge can be varied between 1.5MHz and 4.5MHz. The overall gain is adjustable between 0dB and 42dB and the whole structure only needs 25µA at 900mV supply voltage. The filter is implemented in a 28nm CMOS technology. The design was verified by post-layout simulations.
A distributed amplitude control loop for VCO-array-based EPR-on-a-chip detectors
This paper presents an amplitude control loop (ACL) for VCO-array-based electron paramagnetic resonance (EPR) detectors. The proposed ACL enhances the microwave magnetic field (B1) stability over the whole VCO frequency sweep range, against different sample environments and at varying experimental conditions. By introducing a distributed amplitude detection scheme, the proposed ACL implementation can regulate B1 field intensities in injection-locked VCO arrays with reduced loading effects and minimal phase noise degradation. Extracted-level circuit simulations on an example VCO array implementation demonstrate the functionality and excellent achievable performance of the proposed approach.
|09:15-10:30||B1 | Manufacturing and Testing|
Chair: Elisabetta Moisello, University of Pavia, Italy
Defect Detection in Double-Sided Cooled Power Modules by Structure Functions
This paper presents an approach based on structure functions aimed to the fault detection in state-of-the-art double-sided cooled power modules. The investigation is conducted by means of highly detailed 3-D finite-element method thermal simulations on the exact replica of a power module. Typical defects are emulated ad-hoc in the numerical environment: solder delamination, detached interconnections, and voids/bubbles in the thermal interface material. It is demonstrated that assigned defects give specific shapes to the structure functions; once these shapes are classified, the nature of the defects can be easily unraveled from experimental data.
A Study on ESD-CDM Cross Power Domain Failures
A study about Electrostatic Discharge - Charge Device Model (ESD-CDM) phenomena met in cross-power domain architectures is presented in this paper. The emphasis will be on the limitations of a protection method based on Grounded Gate NMOS (ggnMOS) device with different geometries in an advanced technology node. The considered CDM stress levels varied from 500V up to 2000V. The investigation is based on a test-chip implementation with all the designed architectures. For the recommended 500V CDM stress, a good protection is offered by a ggnMOS structure with channel length increased with at least 50% of the minimum value, in combination with any width in range of 120nm - 1µm.
Manufacturing of silver-ink micrometer inductors through multilayer D.O.D. printing for VHF Power Transfer
Silver ink tracks features deposited through piezoelectric Drop-on-Demand printing thanks to an innovative State-of-Art printer are descripted. Precise printing-trajectories are implemented to limit tracks width and to increase thickness with the purpose of manufacturing high-conductivity spirals in order to create inductors for Very High Frequency power transfer applications. More layers are deposited onto Polyimide without provoking noticeable track width variations. The described printing methodology enabled a rapid and effective thickness increase, essential to manufacture high quality components characterized by low values of sheet resistance together with high values of quality factor.
Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors
Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.
|09:15-10:30||C1 | Physical design and layout-aware synthesis|
Chair: Francisco Fernandez, Instituto de Microelectronica de Sevilla, Spain
ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage
Deep learning (DL) models are now a reality towards the automation of the placement task of analog integrated circuit (IC) layout design, promising to bypass the limitations of existing approaches. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, and symmetry island (SI) constraints are described, and an unsupervised loss function is used for the artificial neural network (ANN) model to learn how to generate placements that follow them. As only sizing data is required for its training, it discards the need to acquire legacy layouts containing insights of these types of constraints. The model is ultimately used to produce floorplans from scratch, at push-button speed, for state-of-the-art analog structures, including technology nodes not used for its training.
Layout-Aware Analog Optimization using Template-based Estimates in Generators
Analog design is very challenging as much information is missing in early design phases. Therefore, worst-case estimates are usually applied which results in overdesign and, thus, waste of area and power consumption. Moreover, simulation of almost final designs is extremely computational expensive usually avoiding iteration loops. In order to enable both early performance estimates and fast iteration runs, we combined parasitic layout estimation through templates in generators with SystemC-based parameterizable modelling. As the result, we can run layout-aware performance estimates of a capacitive pipeline ADC within a runtime of only about one minute per iteration. Using this estimation in a loop, we analyzed and optimized the generator parameters of a capacitor array in order to improve the ADC’s performance.
On Optimizing Capacitor Array Design for Advanced Node SAR ADC
Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-digital converter (ADC) is an attractive design choice for low-power ADC implements. In analog layout design, the parasitics induced by interconnecting wires and elements affect the accuracy and performance of the device. Due to the requirement of low-power and high-speed, the series of lateral metal-metal very small capacitor units as the architecture of capacitor array is usually adopted. Besides power consumption and area reduction, the parasitic capacitance would significantly affect the matching properties and setting time of capacitors. This work presents a framework to synthesize good-quality binary-weighted capacitors for custom advanced node planar SAR ADC. Also, this work proposed a parasitic-aware ILP-based routing algorithm, which can generate an optimized layout considering parasitic capacitance and capacitance ratio mismatch simultaneously. The experimental result shows that the effective number of bits (ENOB) of the layout generated by our approach is comparable with manual design and other automated works.
A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC
In this paper, we propose a new placement technique that takes advantage of the multi-tiers feature of 3D technology to increase the reliability of 3D designs. The proposed algorithm performs a transient effect analysis to identify the error-sensitive sequential components of the design. These components are allocated in the inner tier to reduce the soft error susceptibility of the circuit, exploiting the shielding effect of the outer tier on reducing the SEU cross-section of the component of the inner tier and performing an oculate placement to reduce the effect of secondary transient pulses. Experimental analyses performed by simulation on different benchmark circuits demonstrate the reduction in radiation-induced error sensitivity.
|09:15-10:30||D1 | Special Session - Spotting the gap in the design flow for superconducting electronic devices|
Spotting the gap in the design flow for superconducting electronic devices
Quantum technologies have matured in a way that real applications are considered to be viable. The new quality emerges from the use of explicit quantum phenomena in single objects as qubits for computation, or photons for sensing and communication. However, to make these features exploitable, suitable microelectronic components for controlling and read- out of the quantum states have to be available. For this, superconductive solid-state electronic circuits are considered to be promising candidates. First demonstrations for suitability are known. In order to provide scaling towards large-scale integrated structures, appropriate design methods and capabilities have to be developed. We provide an assessment of the current state of design automation for such superconducting digital electronic structures and survey existing approaches and tools.
|11:00-12:15||A2 | SPAD-based Circuits|
Chair: Alfio Dario Grasso, University of Catania, Italy
Three-wavelength SPAD-based photoplethysmography
For the early diagnosis of cardiovascular diseases, continuous and real-time monitoring of cardio-respiratory signals by portable and accurate instrumentation is very important. Thus, we aim to present a novel photoplethysmography device to assess changes in blood oxygen saturation and beat-by-beat pulse waves of finger blood volumes not affected by possibly occurring changes in oxygen saturation. For this purpose, our device works at three light wavelengths simultaneously and is based on a Single-Photon Avalanche Diode to evaluate the feasibility of contact photoplethysmography by this type of technology. Our preliminary validation shows that the device is robust against movements artifacts and provides measures that reflect the physiological cardiorespiratory adaptations to the Valsalva maneuver, suggesting its overall reliability and possible use in cardiovascular monitoring.
Design Algorithm for N-bit Input Parallel Counters in Application to dSiPM Readout
This work is concerned with the definition of an algorithm for the design of fast parallel counters suitable for counting 1's in large arrays of binary signal sources. One example of such systems is the silicon photomultiplier (SiPM), consisting of an array of SPADs (single photon avalanche diodes) each one providing a high output level when hit by a photon. The paper, besides describing the algorithm, will present and discuss a set of computational tools for estimating the design parameters of interest, such as area, power and delay, as a function of the number of cells to read out.
The Negative Impact of Anode Resistance on SiPM VLC Receivers
The process used to detect individual photons in passively quenched Silicon Photomultipliers (SiPMs) creates a nonlinear response. A model is presented to show this nonlinearity is an unavoidable consequence of microcells recharging after a detection. However, results are presented which show the nonlinearity is increased by the inclusion of an anode readout resistor. Removal of this resistor improves ambient light performance of communication links by a factor of 1.9 under 300 mWm-2 of total 405 nm irradiance.
Comparison of background-rejection techniques for SPAD-based LiDAR systems
We present the results of Montecarlo simulations and measurements focusing on the analysis of two techniques aimed at reducing the negative effect of background light in SPAD-based LiDAR systems. The first technique, known as photon coincidence technique, exploits the temporal proximity of multiple detections to reject background light and maximize the detection of photons belonging to the target reflection. The second technique, named Auto-Sensitivity (AS) technique, reduces the photon-detection probability (PDP) if a certain background illumination level is detected, to avoid the risk of saturating SPADs due to intense background level. The two methods are first compared to each other, showing that the photon coincidence technique outperforms the AS technique. Then, the two techniques are operated together, resulting in an increase of the maximum achievable measurement range if the AS technique is applied on top of the photon coincidence technique.
|11:00-12:15||B2 | Sensors I|
Chair: Vincenzo Stornelli, University of L'Aquila, Italy
Planar Capacitive Transducers for a Miniaturized Particulate Matter Detector
Planar capacitive transducers represent a widespread approach in various sensors since they are amenable to be integrated onto the same die of the electronic front end. The conventional interdigital topology is usually adopted due to its inherent simplicity and modularity. In this paper we explore unconventional topologies of planar capacitive transducers in order to optimize capacitance variation in a fully-integrated CMOS capacitive airborne particulate matter detectors. Simulations show that the circular concentrical topology exhibits the best performances for PM10 detection irrespectively of the particle distance
Quantum Dots for Explosive Detection in Air - Two Complimentary Approaches
With the threatening increase in explosive -based terrorism against civil populations, the development of new devices capable of a rapid and cost-effective detection of hidden explosives has become a worldwide priority. Recently, semiconductor quantum dots have demonstrated great potential as luminescent probes for trace explosive detection. However, the growing interest in this technology and its potentiality is not accompanied by its widespread use in practical applications and in operating environments since most of the proposed devices still consist of lab-based procedures not amenable for field operation. This work explores and compares two alternative ways of employing quantum dots as sensing material to build simple, compact, and reusable devices for vapor explosive detection, beyond their typical use as fluorescent probes in solution. First, a high-performance chemiresistive sensor whose electrical resistance changes proportionally to the target gas concentration is proposed. Then, we present an optical system based on the solid-state photoluminescence of quantum dots cast on a silicon substrate. Easy fabrication, portability, low-cost, high sensitivity, and reusability make both the reported devices quite promising not only for laboratory-scale testing but also for practical applications on the field.
Flood monitoring: a LoRa based case-study in the city of L’Aquila
Low Power Wide Area Network (LPWAN) technologies are particularly suited for environmental monitoring applications due to their potential to achieve small and inexpensive Internet of Things (IoT) systems. In this paper, a LoRa based Wireless Sensor Network (WSN) environmental and flood-oriented monitoring system is presented, covering the sensor node design, realization and real world scenario test results. The system is composed of a microcontroller based sensory device, oriented to raw analog data sampling and manipulation, through a LoRa radio interface used to communicate with a LoRaWAN network structure, followed by a remote web section for information analysis and flooding alarm. Waterproof temperature sensors are employed onboard to enhance the environmental monitoring capability. A MEMS accelerometer device allows alert activation in case of structural activity or vandalism. A power management analysis of the WSN node is provided, so to overcome this critical aspect, in LPWAN implementations. The system is oriented to a modular perspective to achieve different sensor interfacing functionalities.
Interface Circuit for Low-Resistance Sensors Based on Noise Cancelling Technique
A resistive sensor is conventionally biased by a voltage divider or a Wheatstone bridge. Applying a precise bias on a low-resistance sensor with these conventional approaches, however, necessarily requires calibration of the components, which is time-consuming and costly for mass production. In this paper, we propose an analog front-end circuit for low-resistance sensors, based on a closed-loop bias circuit with high-impedance output, which does not require any calibration. In addition, after a comprehensive analysis of the bias noise, we introduce a noise-canceling technique, which allows more than 25dB reduction of the bias noise in the complete interface circuit, even in the presence of gain mismatches as large as 5%.
|11:00-12:15||C2 | Variability-aware modeling and design|
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation
This paper addresses the automated parameter extraction of Random Telegraph Noise (RTN) models in nanoscale FET devices. Unlike conventional approaches based on complex extraction of current levels and timing of trapping/de-trapping events from individual defects in current traces, the proposed approach performs a simple processing of current traces. A smart optimization problem formulation allows to get distribution functions of the amplitude of the current shifts and of the number of active defects vs. time.
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF
Traditionally, every source of variability has been regarded as a source of performance degradation to mitigate. However, variability can be a powerful ally in areas like hardware security and counterfeit detection. The concept of Physical Unclonable Function, a key building block in lightweight cryptography, use variability as the entropy source from which to generate secure authentication and identification. And, while many PUF solutions exist that exploit the well-known Time-Zero Variability, the lack of efficient simulation tools in the area of Time-Dependent Variability has left the potential of this type of variability largely unexplored. This paper combines one such simulation tool to design a novel PUF using the Random Telegraph Noise phenomenon as entropy source. Essential design guidelines are provided to improve the PUF quality.
Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors
Automatic simulation-based sizing approaches are essential in designing radio-frequency (RF) integrated circuit (IC) blocks for modern applications. However, optimizations considering process, voltage, and temperature (PVT) corners or layout still pose unprecedented challenges in applying these tools due to the high simulation times and different simulator convergence issues. This paper proposes two different deep learning (DL) models to assist the PVT-inclusive simulation-based sizing process of RF ICs, and more specifically, voltage-controlled oscillators (VCOs). Given specific devices’ dimensions, the 1st model classifies the likeability of the circuit to convergence for nominal and PVT corners, bypassing solutions that will hardly procedure valuable information for the optimization process, while the 2nd model predicts the VCOs’ oscillating frequencies for the aforementioned conditions. The methodology is tested on a state-of-the-art VCO, reducing 19% of the workload of the circuit simulator, ultimately saving almost 5 days of computational effort and with improvement on the optimization result.
Manufacturing Variation Estimation of On Resistance in Power Semiconductors
In semiconductor industry manufacturing new devices is a very complex process, composed of hundreds of steps. To ensure a high yield, design engineers are considering certain manufacturing limits of the devices. Estimation of the yield is not a trivial process as it is influenced by multiple design parameters therefore a detailed modeling of the device and high precision simulation is required. A large amount of simulation is required for this task and performing this analysis on a family of devices results in running thousands of simulations which is a very time consuming process (e.g a single finite element simulation may take tens of minutes). In this paper we propose a yield estimation method based on 3D finite element simulations. The proposed method consists of developing a prediction meta model, which has as inputs the design properties (geometry and material) of a power transistor and estimates On-State Resistance (Ron) of the device. Therefore, with just an initial number of 3D simulation, required for meta model fitting, one can predict Ron yield for an entire family of products in a matter of minutes because running any further simulations is no longer necessary. Our experiments show that we can develop accurate meta models (accuracy >99.8%) with as low as 1300 simulations. Furthermore, this meta model can be used to achieve an optimum parametric yield.
|11:00-12:15||D2 | Improving Power Delivery|
Model of Switched-Capacitor Programmable Voltage Reference: Optimization for Ultra Low-Power Applications
This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVREF). This PVREF topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a-priori evaluation of the system performance. Circuit optimization is carried out with MATLAB and permits SC-PVREF to achieve current consumptions of tens of nanoampere, suitable for ultra low-power applications.
A Seamless and Unified Flow for Robust Development of DC-DC Digital Controllers
State-of-the-art DC-DC converters are very complex IPs featuring a broad range of functionalities, and their development is crucial from the early stage. Digital statemachines are the core of DC-DC controllers, and their design must be carefully taken into account; leveraging our agile approach is possible to ease the whole DC-DC development and finally reduce the time to market. Initially, referring to mobile AMOLED applications, a specific exemplary case of complex DC-DC is presented. An overview of the asynchronous design flow and its importance is depicted, while all the aspects concerning the DC-DC digital controller implementation in each design phase are detailed. Silicon results showing a DC-DC developed with the presented flow are then demonstrated. Finally, considerations regarding potential new features that may be easily embedded within the proposed flow are outlined, paving the future for possible improvement to overcome ever increasing DC-DC challenges.
Control-oriented optimization of the coil pair design in dynamic WPT systems for electrical vehicles
TO BE UPDATED - This paper discusses modeling and design of Series-Series Wireless Power Transfer Dynamic Battery Chargers (SS-WPT-DBCs) for electric vehicles. A model based on dimensionless quantities is proposed, which accounts for the influence of coil pair characteristics and transmitter and receiver power converters control settings on the system performances. The proposed model is used as basis for a design method that provides the coils and control settings allowing to achieve the desired efficiency, receiver power loss and battery charge specifications.
Exploiting Saturable Inductors in SEPIC Regulators
This paper discusses the use of saturable power inductors in Separate Inductors Single-Ended Primary Inductor Converter (SI-SEPIC) regulators. The input and output inductors in SI-SEPIC regulators must be selected with an inductance ratio fitting suitable constraints to ensure the stability, which may lead to large output inductance in applications involving step-up voltage conversion ratio. The method and the results presented in the paper show that using saturable ferrite inductors allows to reduce the size of components, while providing larger inductance in low-load operation that help preventing discontinuous conduction mode and increasing the efficiency. The results are validated by means of simulation tests performed on a 12V/1A SI-SEPIC regulator.
|15:00-16:00||I1 | Industrial Talks I|
Chair: Franco Maloberti, University of Pavia, Italy
Integrated power electronic solutions for a sustainable future (Infineon)
Introduction on Surface Sound Technology (Inventvm)
Company Overview (Power Integrations)
|16:00-18:05||A3 | SMACD EDA Competition|
A Design Flow and EDA-Tool for an Automated Implementation of ASIC Configuration Interfaces
The growing complexity of integrated circuits results in an increasing importance of configuration capabilities. Due to the criticality regarding the overall tapeout success, a fail- safe and error-free implementation of the configuration interface is indispensable. This paper presents a design flow together with a developed EDA-tool to satisfy this reliability demand. Key feature is the replacement of an error-prone manual implementation by an automated generation of pre-verified HDL source code. At the same time, the implementation effort for the configuration interface is significantly reduced.
A Simulation Tool for Space Applications: RadiSPICE
This paper describes a radiation simulation tool, RadiSPICE, which has the capability of performing statistical radiation simulations, temperature sweep, and sensitivity analysis for integrated circuits prone to radiation exposure. Single Event Transient (SET) and Total Ionising Dose (TID) effects are modelled through current and voltage sources introduced to the circuit. RadiSPICE imports the circuit netlist and performs statistical radiation simulation, temperature sweep, and sensitivity analyses. Output histograms along with maximum and minimum values of extracted parameters can be probed. To demonstrate the effectiveness of the tool, two case studies are performed on a linear amplifier and a logic cell, showing that space radiation can be detrimental to electrical circuit performance. To our best knowledge, the developed tool is the first example of a well-equipped CAD tool for radiation simulation for electrical circuits.
Expert Design Plan: A Toolbox for Procedural Automation of Analog Integrated Circuit Design
This paper presents a toolbox in Matlab/Octave for procedural design of analog integrated circuits. The toolbox contains all native functions required by analog designers (namely, schematic-generation, simulation setup and execution, integrated look-up tables and functions for design space exploration) to capture an entire design strategy in an executable script. This script - which we call an Expert Design Plan (EDP) - is capable of executing an analog circuit design fully automatically. The toolbox is integrated in an existing design flow. A bandgap reference voltage circuit is designed with this tool in less than 15 min.
From Image to Simulation: An ANN-based Automatic Circuit Netlist Generator
This study proposes an Artificial Neural Network (ANN) based netlist generator: Img2Sim. The tool acquires an image of an electronic circuit, classifies the existing circuit elements, including active components (MOSFET, BJT, Op-Amp, etc.), with at least 98% accuracy, and decides the circuit topology and the connections with over 90% accuracy through a rule-based algorithm. Finally, it automatically yields a simulation-ready netlist for the circuit of concern. It is worth noting that some CAD tools have been developed before; however, they have mostly focused on recognizing the circuit elements only, and, to our best knowledge, Img2Sim is the first CAD tool that creates the entire netlist for a given circuit in image format.
|16:00-18:05||B3 | Analog Circuits I|
Chair: Salvatore Pennisi, University of Catania, Italy
A 2+1 Hybrid Incremental MASH Converter
This paper explores the possibility of using the MASH (multi-stage noise shaping) technique in incremental converters to be used for x-rays detection, targeting a medium high resolution in a limited conversion time. The presented 2+1 MASH receives at the input a current generated by a photodiode. The adopted scheme is hybrid as the input stage is continuous time while the remaining portion of the circuit operates at discrete time. The converter is studied at the behavioural level in the MATLAB-Simulink environment and some design trade-offs are analysed and discussed in details.
High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain
This paper presents a novel ultra-low-power ultra-low-voltage operational transconductance amplifier (OTA). The OTA operates with a 0.3V supply voltage and shows remarkable bandwidth performance with very limited power consumption, owing to the use of current mirrors with gain. Low impedance internal nodes of the current mirrors allow to boost gain and bandwidth, adding only high-frequency poles to the frequency response. Therefore, the compensation of the proposed OTA can be achieved through a dominant pole at the output, as in conventional cascode amplifiers. The circuit employs two identical input stages with cross-coupled inputs to improve common-mode rejection ratio (CMRR) performance, and a differential-to-single-ended output stage. The resulting architecture achieves a remarkable FOMS value, as demonstrated by the simulations performed in a commercial 130nm CMOS technology.
1-mS constant-Gm GaN transconductor with embedded process compensation
This paper presents the design of a GaN constant-Gm transconductor for smart-power applications. The proposed solution exploits source degeneration to linearize the transconductance and three cascode current mirrors to increase the transconductance and provide differential to single-ended conversion. Moreover, a biasing section is added to cope with the wide process spread, especially in threshold voltages, of both enhancement and depletion GaN transistors. Nominal simulation results show that the proposed transconductor, supplied from 6-V and biased with 655 µA provides 1 mS transconductance, within a linear differential input range of ±100 mV up to more than 10 MHz.
A 0.5-V 28-nm CMOS Inverter-Based Comparator with Threshold Voltage Control
This paper proposes a novel solution for CMOS inverter-based comparators with threshold voltage control. The solution was simulated in a 28-nm bulk technology under 0.5-V supply. Extensive simulation results show that a reasonable accuracy in the threshold voltage setting is achieved regardless PVT variations. Outperformed average current consumption of about 125 nA, excluding reference circuitry, and rise/fall time of 7.9 µs suggest wide field of applications for the proposed circuit, ranging from A/D converters to sensors for biomedical applications.
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation
This paper presents a novel auto-zeroing common-gate comparator. This topology cancels the input-referred offset voltage by AC coupling the gates of the two input mosfets. The circuit operation is divided in two phases: in the first one, the circuit is in closed loop and samples the offset voltage as a voltage difference between two capacitors, while, in the second phase, the circuit is configured in open loop to compare the two input signals. MonteCarlo simulations run on a reference design in CMOS process shows that the offset standard deviation is reduced from 4.42mV down to 25.85uV. The designed comparator shows a 290uW power consumption from a 5V supply, while occupying a total area of 0.0156mm2.
A Triode-Compensated CMOS Bandgap Core for Sub-250 mV Supply Voltages
This paper presents a simple and original CMOS, sub-threshold bandgap voltage reference capable of operating with extremely reduced supply voltage values. The circuit capability is demonstrated by means of accurate electrical simulations performed on a prototype designed with a standard 0.18 um CMOS process. A reference voltage of 190 mV has been obtained with a minimum supply voltage of only 223 mV and a line regulation close to 8 mV/V.
Behavioural Current Limiter Optimisation
In this paper an optimisation procedure based on a Behavioural model (developed in the MATLAB and Simulink) of a current limiter circuit is presented. Through the behavioural environment a coarse design optimisation is performed, while fine optimisation is later performed at transistor level. The proposed approach reduces design time compared to a full transistor level design procedure. Once the behavioural model reliably fits the transistor level behavior, any optimisation algorithm can be used in the MATLAB environment to adjust behavioural model parameters. The Current limiter case adopted as benchmark in this work demonstrates how control-loop stability can be improved through the parametric study of the loop frequency response and can be optimized by the insertion of an additional zero in the circuit transfer function.
|16:00-18:05||C3 | Sensors II|
Chair: Giuseppe Ferri, University of L'Aquila, Italy
PixiStamp: A tool to acquire, process, and sequence AER data from event-driven systems
We present a new tool, PixiStamp, to readout, process and sequence data of event-driven systems that exchange data using the Address Event Representation (AER) protocol.PixiStamp is a compact acquisition board that can be easily attached to other devices. Over other existing solutions, it has enhanced hardware processing capabilities to process AER data and generate control signals after data processing, making possible a closed-loop device control. The article describes in detail the system architecture, its mechanical design, and its main features.
A Compact Embedded System for Time-Based Electrochemical Impedance Spectroscopy of Gas Sensors
In this work, a compact embedded system for timebased EIS of gas sensors is presented. Differently from other works, which rely mostly on laboratory instrumentation, the proposed system proves that fast EIS measurements can be implemented on reduced size hardware with minimal employment of on-board components. These goals are achieved thanks to the implementation of the MLS-based measurement technique on a programmable system-on-chip (PSoC) device. In particular, the IR of the sensor is measured by driving it with an MLS excitation signal, thus performing the digital cross-correlation between the input and the output. The selected PSoC device allows the implementation of the digital circuits, the microcontroller and the analog front-end in the same device. As a benefit, the bill of on-board components is extremely reduced. The system architecture and operation are presented in detail and the experimental measurements, obtained by testing a parallel RC as sensor circuit model, are showed. The accuracy between different measurements is evaluated by computing the Pearson’s correlation coefficient for each measured IR.
A 55nm Low-Noise Super-Source-Follower Preamplifier for MEMS Microphones
In this paper a low-power, low-noise interface for Micro Electro-Mechanical System (MEMS) silicon microphone built in a 55nm MOSFET technology is presented. The designed interface is made up by a pseudo-differential structure, based on two single-ended Super-Source-Followers with PMOS input device, to reduce Flicker noise contribution that would affect low frequency applications. The challenge of this design regards the implementation in 55nm of high performance analog cells. The device performs output integrated noise in the [20Hz - 20kHz] audio band of about -110dBV(A), with a total power consumption of 270µW from a 1.5V voltage supply. Acoustic Overload Point (AOP) reaches a mean value of 130dBspl.
On the implementation of in-pixel controlled diodes with sensing and energy harvesting capabilities
Energy harvesting plays a crucial role in low-powersystems and Internet-of-Things (IoT) sensing nodes. Measuringthe illumination level of the scene is desired in such applications.Few studies have explored the possibility of designing imagesensors that use photodiodes to harvest energy from the sceneto reduce consumption or even achieve a self-powered operationusing frame-based approaches. This work aims to validate theswitching capabilities of photodiodes independently within aphotodiode array. While most studies focus on alternating theharvesting and sensing operation in two different phases, inthis approach a fraction of the photodiodes are connected toa global node to harvest energy, while the rest are sensing.This configuration qualifies to design asynchronous imagers andoptimize the harvesting operation. The preliminary experimentalresults reported in this publication emphasize the validity of thisasynchronous switching in photodiode arrays.
Optimization and characterization of inkjet printed interdigitated electrode geometries for impedance measurements
There is an increasing demand for continuous monitoring of biochemical parameters. Such applications require label-free sensing techniques which can be implemented on a variety of substrates. An impedance spectroscopy-based technique, using interdigitated electrodes is described. The electrodes with different geometrical parameters are fabricated by inkjet printing of silver nanoparticles on a flexible polyethylene substrate. The electrodes geometries differ in their metallization ratios. Impedance measurements are performed with DI water to determine the influence of metallization ratio on the electrode capacitance. From these results, the electrode that offers the highest capacitance is further characterized by measurements with ethanol-water mixtures. The results show that there is a decrease in capacitance of 0.1 pF per % increase of ethanol concentration. This is due to the decrease in permittivity as the ethanol concentration increases. The sensor is sensitive to the changing permittivity values. Therefore, an impedance based, label-free, sensor concept on flexible substrate has been implemented.
Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array
The large number of data generating sources (data channels) on a single chip requires appropriate techniques to manage a readout from these channels. One of the main methods is sharing a medium of transmission, which requires arbitration to avoid collisions or deadlocks. Existing solutions face several problems such as a dead time, unintended prioritization or metastability. That is why we decided to create a new readout architecture named EDWARD i.e., Event Driven with Access and Reset Decoder. The EDWARD architecture gets rid of the earlier mentioned problems and mitigates the other ones. However, due to the use of logic circuits outside a standard cell library, which are hard to characterize, we were challenged to perform an additional transient analysis to validate the architecture. Here we show a methodology and the results of the simulations. Based on the results obtained we can confirm the functional correctness of the system and plan the optimization of operating conditions in order to achieve better performance. Our goal is to use the EDWARD architecture in the future radiation detectors to be built at Brookhaven National Laboratory.
Centroid estimation method with sub-pixel resolution for event-based sun sensors
A new method to obtain sub-pixel measurement resolution for sun sensors based on spiking pixels is presented. The procedure is intended to increase the resolution of the estimated angle. The method uses the profile of incident light to estimate the angle of the vector towards the sun with sub-pixel resolution. Read-out time, data bandwidth, and spatial resolution are improved. Experimental results are provided. The proposed method can be implemented in any asynchronous sun sensor operating in Time-to-First-Spike (TFS) mode.
|16:00-18:05||D3 | Digital Circuits I|
Chair: Patrick Haspel, Synopsys, Germany
Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor
In this paper we assess the performance of the new MATLAB Deep Learning Processor. It is a hardware architecture meant for FPGA devices which is able to infer Convolutional Neural Networks. The system is deployed on a Xilinx ZCU102 SoC and we customize it with the aim to maximize its processing performance. We evaluate the hardware resources utilization, the maximum achievable clock frequency, and the power dissipation of the system. Our goal is to find the best performing networks on FPGA and, eventually, to compare the results with a GPU-based counterpart. We conduct an experimental campaign where the FPGA execution time of several CNNs is profiled and compared to the execution time on the NVIDIA Titan RTX GPU platform. This allows a comparative performance analysis when the same network is inferred on different systems. We consider all the available CNNs of the MATLAB suite which have been pretrained with the ImageNet dataset. Finally, to pinpoint the most cost-effective network, the FPGA prediction time is put in relation with the accuracy on the aforementioned dataset.
A 0.63 pJ/bit Fully-Digital BPSK Demodulator for US-powered IMDs downlink in a 28-nm bulk CMOS technology
Battery-less implantable medical devices (IMDs) are encountering an always growing interest in recent years. The ability to control body-organs activities using electrical stimulators requires the establishment of a Data Down-Link, while a Data Up-Link is an ubiquitous feature to monitor health conditions by acquiring biological signals. Under this scenario, this work deals with the design and the simulations of a Fully-Digital Binary Phase-Shift Keying (BPSK) demodulator for the Downlink in Ultrasound (US)-powered IMDs. The system presents low area occupation, ultra-low power consumption down to 1.25 μW. It is implemented in a 28-nm bulk CMOS technology provided by TSMC. Its data rate rises up 2 Mbit/s and a minimum energy-per-bit equals to 0.63 pJ/bit.
Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA
This paper presents a multi-exposure fusion approach suitable to be hardware implemented and integrated in real-time video processing pipelines. The proposed approach is inspired by the Merten’s algorithm for blending images in a multi-exposure sequence through simple quality measures, such as saturation and contrast. However, for the purpose of a hardware-friendly implementation, complex Laplacian and Gaussian pyramid computations are here replaced with simpler operations. The proposed approach is suitable to be integrated within a complete system targeting heterogeneous FPGA SoCs. When implemented within the Xilinx Zynq XC7Z020 chip, it runs 94 Mega pixels per second and occupies just 18493 LUTs, which is at least 25% faster and 35.5% cheaper than state-of-the-art designs.
Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition
Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessary overuse of resources or is hardly possible to meet. The latter case is typical of incompletely specified synthesis problems, targeting the hardware implementation of a Boolean function from a partial knowledge of its care set. The missing elements of the care set are named "don't knows". Previous works identified information theory-based decomposition strategies as powerful synthesis tools. Nonetheless, the definition of an automatic method for approximate synthesis is an open problem, and the approximate counterpart of many logic synthesis techniques is still missing. In this paper, we extend a disjoint support decomposition algorithm to target Boolean functions in the presence of "don't knows". Furthermore, we integrate the decomposition in an information theory-based synthesis flow. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to the flow reduces by 15.63% the number of gates and by 12.22% the depth.
Approximate Recursive Multipliers Using Carry Truncation and Error Compensation
Approximate computing is a fast-emerging paradigm promising higher circuit performances in error tolerant applications. Binary multipliers are a common target for approximate computing due to their complexity and the multitude of their applications. In this paper, we investigate approximate recursive multipliers based on novel 4x4 multiplier blocks. We present three approximate 4x4 multipliers, with different error-precision trade-off, obtained by carry truncation and error compensation. These basic blocks are exploited to design 8x8 approximate multipliers. The proposed circuits are implemented in a 14 nm FinFET technology and show improved performance compared to the state-of-the-art.
Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions
Transposed convolution is a crucial operation in several computer vision applications, including emerging Convolutional Neural Networks for super-resolution, generative adversarial and segmentation tasks. Such algorithms deal with high computational loads and memory requirements, which hinder their implementation in real-time and power-constrained embedded systems. In addition, they may adopt different kernel sizes along the network, thus making the design of flexible yet efficient hardware architectures highly desirable. This paper presents a reconfigurable accelerator able to runtime adapt its computational capabilities to perform transposed convolution with different kernel sizes. When accommodated within the Xilinx XC7Z020 and XC7K410T chips, the proposed design dissipates less than 95 mW at 125MHz and 179 mW at 250MHz, exhibiting a throughput of 1.95 and 3.9 Giga output per second, respectively. Both the implementations overcome state-of-the-art counterparts, achieving an energy efficiency up to 4.4 times higher. When used to accelerate the Fast Super Resolution Convolutional Neural Networks, the novel reconfigurable architecture achieves an energy efficiency at least 23% better than the competitors.
Interaction between forming pulse and integration process flow in ePCM
Ge enrichment of the GeSbTe (GST) chalcogenide made possible for embedded phase change memories (ePCM) to guarantee the retention level necessary to satisfy the automotive market’s requirements. In Ge-GST devices at the end of the fabrication process memory cells are in the pristine state (virgin) and, in order to be programmed, an activation step is necessary (forming). In this work an investigation on the influence of two back end of the line (BEOL) processes on the virgin state and forming process is presented. A model that accurately replicates both physical and electrical trends is also shown.
|Tuesday, June 14th|
|09:00-10:30||A4 | RF Circuits and Systems II|
Chair: Michael Peter Kennedy, University College Dublin, Ireland
Linearity Analysis of BiCMOS Coherent TIAs
The linearity of a coherent TIA for optical transceivers is studied. The goal of the transimpedance gain is 74dBΩ. The study of the design parameters that limit each block's linearity provides design directions for a TIA with THD equal to or lower than 1%. The analytical study uses the Ebers-Moll model and achieves design criteria confirmed by transistor-level simulations, carried out using a 130nm BiCMOS process.
A 1.1-to-2.7 GHz CMOS Power Amplifier with Digitally-Reconfigurable-Impedance Matching-Network (DRIMN) for Wideband Performance Optimization
This paper presents a wideband CMOS power amplifier (PA) with Digitally-Reconfigurable-Impedance-Matching-Network (DRIMN) which is utilized to tune the impedance of the PA and also to optimize its performances across the frequency. The proposed DRIMN-PA is employed at the input, interstage, and output matching networks to establish a complete impedance tuning mechanism at all stages of the PA. The DRIMN mechanism comprises switching capacitors and inductors which are controlled via digital switching bits. The tuning property of the tunable inductor is executed via switching of multiple secondary windings that are employed in between the turns of the inductor’s winding. The tunable inductor is designed area-efficiently in which the secondary windings do not consume large area on-chip. The DRIMN-PA is fabricated in CMOS 130 nm process and has an operating bandwidth of 1.6 GHz from 1.1 to 2.7 GHz. It delivers a maximum output power of 27.5 to 28.5 dBm with peak PAE of 34 to 40% after tuning the RDIMN mechanism. The DRIMN-PA is also measured with a 20 MHz LTE modulated signal in which the attained linear output power and PAE are 23.3 to 24.8 dBm and 33 to 38%.
A Compact C-band EPR-on-a-chip Transceiver in 130-nm SiGe BiCMOS
We present a chip-integrated C-band transceiver for electron paramagnetic resonance (EPR) spectroscopy, implemented in a 130-nm SiGe BiCMOS technology. The presented EPR-on-a-chip transceiver displays an excellent minimum in-band noise figure of 0.82 dB and a peak in-band output power Psat of 9.8 dBm. Furthermore, the presented chip provides a wide frequency operating range from 6 GHz to 8 GHz, which is crucial for detecting wideband EPR signals. The receiver and two-stage four-way combined power amplifier provide (conversion) gains of 32.8 dB and 13 dB, respectively. In proof-of-concept EPR measurements using an off-chip PCB coil as detector and the standard EPR sample BDPA, the presented chip achieves a competitive spin sensitivity of 8×10^10 spins/√Hz over an active volume of 31 nl.
An Ultra Low-Voltage RF Front-end Receiver for IoT Devices
This paper presents the design of an RF receiver front-end for IoT application, integrating a low noise amplifier (LNA) and an active mixer. The front-end is designed in 28-nm FD-SOI technology, to operate on the ISM 2.4−2.5 GHz band. The inductor-less LNA exploits the parasitic package inductance as resonant load, limiting chip area and costs. The receiver, designed for the stringent requirements of the application, operates with a voltage supply of 0.35 V, and it exhibits in simulation a power consumption below 45 μW. Besides, it achieves a voltage gain of 27.4 dB, a Third Order Input Intercept Point (IIP3) of -26.8 dBm, and a noise figure (NF) of 12.8 dB, with an intermediate frequency (IF) of 2 MHz. The small area of only 0.0021 mm2, combined with the low power consumption and operating voltage, make the proposed RF receiver well-suited for the IoT application domain.
Retrodirective Rectenna Arrays for passive SHF-RFID Transponders
In this work we combine the retrodirectivity of Van Atta arrays with the direction-independent power reception capability of rectenna arrays to compensate for the high free-space path loss in the super high frequency (SHF) band. Currently the range of SHF systems using modulated backscattering at passive transponders is limited by this effect. To overcome this problem we propose a new array structure connecting multiple antennas and rectifiers through a passive network. By using the proposed approach on an N × N array, energy and backscatter range can both be increased by a factor of N. This enables radio frequency identification (RFID) systems in the SHF band to achieve similar coverage as ultra high frequency (UHF)-RFID systems, while gaining the advantage of higher available bandwidth. Influences from the direct environment of the transponders can be compensated for and the possibility of high accuracy transponder localization arises.
|09:00-10:30||B4 | Human Monitoring and Detection Systems|
Chair: Antonio Aprile, University of Pavia, Italy
Heterogeneous FPGA-based System for Real-Time Drowsiness Detection
Drowsiness detection is a key feature in modern Advanced Driver Assistance Systems (ADAS). State-of-the-art approaches rely on machine learning techniques and neural networks to monitor unusual movements of the head and eyes activities. Unfortunately, due to their computationally intensive operations, integrating such algorithms in real-time and low-power operating scenarios, like automotive applications, is still quite challenging. This paper proposes an efficient hardware architecture for real-time drowsiness detection based on monitoring the driver’s eye blinking behaviour through the PERcentage of eye CLOSure (PERCLOS) metric. Experimental results obtained on the Xilinx Zynq XC7Z020 FPGA SoC show that the proposed system is up to 33.3 times faster and 2.6 times less area consuming than state-of-the-art competitors.
Two-stage Human Activity Recognition on Microcontrollers with Decision Trees and CNNs
Human Activity Recognition (HAR) has become an increasingly popular task for embedded devices such as smartwatches. Most HAR systems for ultra-low power devices are based on classic Machine Learning (ML) models, whereas Deep Learning (DL), although reaching state-of-the-art accuracy, is less popular due to its high energy consumption, which poses a significant challenge for battery-operated and resource-constrained devices. In this work, we bridge the gap between on-device HAR and DL thanks to a hierarchical architecture composed of a decision tree (DT) and a one dimensional Convolutional Neural Network (1D CNN). The two classifiers operate in a cascaded fashion on two different sub-tasks: the DT classifies only the easiest activities, while the CNN deals with more complex ones. With experiments on a state-of-the-art dataset and targeting a single-core RISC-V MCU, we show that this approach allows to save up to 67.7% energy w.r.t. a "stand-alone" DL architecture at iso-accuracy. Additionally, the two-stage system either introduces a negligible memory overhead (up to 200 B) or on the contrary, reduces the total memory occupation.
Differential Impedance Biosensing platform for early diagnosis of viral infections
Detection of viruses is essential for the control and prevention of viral infections. In recent years, there has been a focus on simpler and faster detection methods, particularly through the use of electronic-based detection in a point-of-care configuration. The proposed biosensor platform can provide high-resolution measurements of viral infections by detecting antibodies. The system is based on differential impedance measurement of the biological target with nanoparticle amplification. The surface of the sensor is biochemically functionalized with a synthetic peptide to mimic the antigenic determinant of the targeted virion particle. Gold interdigitated microelectrodes are the core of the biosensing system. They are designed in a differential configuration, reference and active sensor, to counteract all possible mismatches such as temperature fluctuations and variations in the ion content of the solution. The successful combination of these elements makes it possible to reach a limit of detection of the system below 100 pg/mL for IgG antibodies in buffer. Furthermore, the biosensing system has been challenged with infected human serum samples for digital counts of anti-dengue virus antibodies, achieving the detection of clinically relevant target concentrations.
Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference
Low-resolution infrared (IR) Sensors combined with machine learning (ML) can be leveraged to implement privacy-preserving social distance monitoring solutions in indoor spaces. However, the need of executing these applications on Internet of Things (IoT) edge nodes makes energy consumption critical. In this work, we propose an energy-efficient adaptive inference solution consisting of the cascade of a simple wake-up trigger and a 8-bit quantized Convolutional Neural Network (CNN), which is only invoked for difficult-to-classify frames.
Design of a CMOS Analog Front-End for Wearable A-Mode Ultrasound Hand Gesture Recognition
This paper presents a CMOS ultrasound analog front-end for wearable A-mode ultrasound hand gesture recognition. This analog front-end is part of the research into using ultrasound to record and decode muscle signals with the aim of controlling a prosthetic hand in contrast to the conventional method, surface electromyography. In this paper, the design of a pulser for driving piezoelectric transducers as well as a low-noise amplifier for the received echoes are discussed. Simulation results show that the pulser circuit is capable of driving a 137-pF capacitive load with 30 V pulses at a frequency of 1 MHz and dissipates 142.1 mW power. The low-noise amplifier demonstrates a programmable gain of 10/20/30 and an input-referred noise of 8.68 nV/√Hz at 1 MHz.
|09:00-10:30||C4 | Machine learning applications|
Machine Learning Approaches for Transformer Modeling
In this paper, several machine learning modeling methodologies are applied to accurately and efficiently model transformers, which are still a bottleneck in millimeter-wave circuit design. In order to compare the models, a statistical validation is performed against electromagnetic simulations using hundreds of passive structures. The presented models using machine learning techniques have proven to be accurate, efficient, and useful for a wide range of frequencies from (around) DC up to the millimeter-wave range (around 100GHz). As an application example, the models are used as a performance evaluator in a synthesis procedure to optimize a transformer and a balun.
Advanced Operating Conditions Search applied in Analog Circuit Verification
Integrated Circuits (ICs) are now very complex systems with a huge number of components integrated in a single design. As a consequence, pre-Silicon (pre-Si) analog IC verification, whether module-level or system-level, is an extremely time-consuming task. Verification in all possible operating condition (OC) configurations is practically impossible, due to the high number of OCs and the huge size of the OC hyper-space. In this context, advanced sampling methods for the OC hyper-space are required to offer better coverage with a smaller number of simulations. In addition, machine learning (ML) surrogate models are proposed to be used instead of time-consuming circuit simulations. In this context, we propose and evaluate several advanced sampling methods for the OC hyper-space and show that they provide results similar to the classical verification approach using 3x less simulations. Moreover, we show that training a ML surrogate model on this data leads to a much more effective model, that can be subsequently used to identify the circuit’s actual worst cases.
Learn from error! ML-based model error estimation for design verification without false-positives
Behavioral models are important tools for electronic system-level design and verification due to their simplicity and fast computing time. However, this simplicity is a double-edged sword as it introduces model errors that are hard to keep track of. In this paper, we present an approach to estimate the model error of behavioral models by utilizing an artificial neural network. This can be integrated into system-level simulations and provides online, reliable information on the validity of the model. Knowing the model error allows to evaluate trade-offs by tolerating errors where possible and ensuring precision where needed. Considering computing time, the proposed approach is low cost and aides the designer to balance speed and precision in the behavioral modeling of complex circuits. To demonstrate the capabilities of this approach, we showcase the performance in a case study.
Framework for Developing Neural Network Regression Models Predicting the Influence of EMI on Integrated Circuits
In this paper we present a framework to develop regression models that predict the behaviour of integrated circuits (ICs) when exposed to electromagnetic interference (EMI). To do so, we use techniques that are commonly used in artificial intelligence (AI) applications. We show, how to create data sets from simulation, how to split these into training and test data, and how to pre-process these. Further on, we explain which AI models are suited best for predicting changes due to EMI. We also elaborate the structure and complexity of these models with regard to the model’s capability to fit the training and test data. We implement this framework using the Tensorflow library in Python and explain its application on an example predicting the EMI induced offset voltage. Therefore, we provide the data sets as well as the source code of the framework.
Applications of Machine Learning Techniques for the Monitoring of Electrical Transmission and Distribution
This paper shows some application examples of machine learning techniques in the monitoring of electricity distribution services. In particular, the application of neural network-based techniques is considered in two different areas of interest: monitoring of underground cables in medium voltage lines and fault diagnosis of joints in overhead electrical lines (high voltage).
|09:00-10:30||D4 | Characterization and analysis of variability phenomena|
Accelerating Electromigration Stress Analysis Using Low-Rank Balanced Truncation
Electromigration (EM) has become one of the most significant challenges considering longterm reliability in Integrated Circuits (ICs) design. The problem is induced by the large current density in circuit interconnections. However, in most cases, EM stress is more pronounced in the vias and the blocking points of the interconnects. As a result, Model Order Reduction (MOR) techniques can provide attractive methodologies to reduce the complexity of the original systems. System-theoretic techniques like Balanced Truncation (BT) offer very reliable bounds for the approximation error, compared to moment-matching methods. In this paper, we apply a computationally efficient low-rank BT algorithm based on the extended Krylov subspace method, that can handle large-scale models and significantly accelerate the EM stress analysis. Experimental results on the industrial IBM power grid benchmarks demonstrate that our method can achieve a speedup up to 238x over a standard transient analysis method and a speedup up to 15x over COMSOL, while exhibiting negligible error.
Impact of Process Variations on the Performance of a Widely Tunable CMOS Transconductor
The methodology followed to determine the impact of process variations on the experimental behavior of a widely tunable transconductor, is presented. The principle of operation of the linearized transconductor is based on subtracting the responses of two matched voltage-to-current converters. As a result, the simulated transconductance of the cell can be continuously tuned over around three decades, from 27.96 uA/V to 33.6 nA/V. The circuit has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8 V supply. The experimental characterization of 8 samples of a silicon prototype reported a measured range of the transconductance between 20.57 uA/V and 1.42 uA/V. Montecarlo and corner simulations have been carried out to ascertain the origin of this noticeable deviation.
Characterization and analysis of BTI and HCI effects in CMOS current mirrors
This paper presents experimental results on the aging-induced degradation of CMOS current mirrors fabricated in a 65-nm CMOS technology. A dedicated integrated circuit array with custom test structures allowing for accelerated aging tests is used for the characterization, including several geometries of simple current mirrors, in PMOS and NMOS versions. The bi-directional link between device degradation and bias conditions that comes into play during circuit aging, as well as the permanent degradation, are both reported and analysed.
Impact of BTI and HCI on the reliability of a Majority Voter
Triple Modular Redundancy is a commonly used hardware technique in mission- and safety-critical systems to ensure reliability. Although a simple circuit, the majority voter can be the weak link in this system and different designs have been proposed to increase its robustness to single event effects and permanent faults. However, no study has been performed to analyze the effect of BTI and HCI on a majority voter, which can lead to timing failures or exacerbate other failure mechanisms. This work uses a state-of-the-art aging simulator to estimate the effects of aging on a majority voter.
|11:00-12:15||I2 | Industrial Talks II|
Chair: Edoardo Bonizzoni, University of Pavia, Italy
Welcome to the future, welcome to ST (STMicroelectronics)
15 years of evolution in High-Speed SerDes: why is this design still so attractive? (Synopsys)
Shape the future with Bosch sensors (Bosch)
|14:30-15:30||T1 | Tutorial I|
State of the art cosimulation methodology with Cadence® Virtuoso®/Spectre-RF® and MathWorks® MATLAB®/Simulink®
|15:30-16:30||I3 | Industrial Talks III|
Ahead Of What’s Possible (Analog Devices)
Huawei & Research: leveraging university to support digital transformation (Huawei)
Photeon Technologies GmbH (Photeon)
|16:30-18:35||A5 | Analog Circuits II|
Chair: Edoardo Bonizzoni, University of Pavia, Italy
A Low-Power, Short Dead-Time ASIC for SiPMs Readout with 200 MS/s Sampling Rate
FALCON readout channel for X-ray ptychography applications
This work reports the current state of the development of a pixelated readout for nanometer resolution X-ray ptychography applications. A very dense, low-noise and low-power pixel developed in a commercial 65 nm CMOS technology is envisioned for such applications, targeting a pixel area of 150 μm x 150 μm, an overall noise of 200 e- rms and a power consumption of 150 μW per pixel. In the paper, an introduction to the application and an overview of the experimental setup are given, the designed front-end channel is reported and revised in its components and simulation results of the schematic-level design are shown and discussed.
16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency
Fast fourier transform (FFT) is indispensable in multi-carrier radio frequency transform systems, especially in the Orthogonal Frequency Division Multiplexing (OFDM) system.And almost all transform systems implement FFT algorithms in the digital domain.Compared with the realization in digital domain, the implementation in analog domain brings greater advantages in speed and power consumption.This paper proposes a new type of analog Fast fourier transform (AFFT) system, analyzes the algorithm choice and compares the advantages and disadvantages of different algorithms, sets up the system model with non-ideal factors, constructs the specific circuit and compares the performance with different systems.
A 3-decade-frequency-range Sinewave Synthesizer with Analog Piecewise-linear Interpolation
In this work, we present a novel approach for the on-chip synthesis of sinusoidal signals for low-size and lowpower applications. The original aspect of the proposed solution is the ability to generate linearly interpolated signals by means of analog interpolation. This gives rise to notable distortion performances with a low circuit complexity. The potentiality of the proposed approach was verified by means of electrical simulations performed on a prototype designed with a standard 0.18μm CMOS process. A THD as low as 0.59%, calculated considering also the aliasing effect implied by the linear interpolation, was obtained at a 100 kHz sinewave frequency. The power consumption is around 300 μW. The possibility of varying the sinewave frequency in a 3-decade wide range was also assessed. Results obtained from 50 Monte Carlo runs at f0 = 100 kHz indicated a worst-case THD around 1.3%.
Design and Characterization of an Active Low-Pass Envelope Detector for Wake-Up Radio Receivers
This paper presents a design flow for an active low-pass (LP) Envelope Detector (ED) for Wake-Up Radio (WUR) receivers and provides insight on the well-known bitrate-sensitivity-current trade-off and on additional aspects which may be critical in Internet of Things (IoT) applications, such as maximum receivable input power and robustness against Continuous Wave (CW) interferers. The implemented LP ED, designed using the STMicroelectronics 90-nm BCD technology, receives 400-bit OOK-modulated packets with an 868-MHz carrier frequency and achieves -35.5-dBm sensitivity with a 4.5-nW power consumption. Finally, it receives input power levels up to 15 dBm and achieves 22-dB Signal-to-Interference Ratio (SIR) with a CW interferer with a 100-kHz frequency offset.
Design and Optimization of a vibrational-MEMS based energy harvester
The study conducted shows a Vibrational Energy Harvester (VEH) based on a microelectromechanical system (MEMS) with a gap-closing electrostatic resonator. The system is validated and implemented by Cadence Virtuoso. Then, the electrical signal from the MEMS is rectified with a pump circuit based on the Greinacher voltage doubler. The rectifier was designed using 0.18 μm technology. Finally, the optimal resistive load of the system is calculated and implemented to calculate the optimal range of operation and its generated power through a load resistor. The implemented energy harvester generates a DC power output of 90.06nW at 9.95V under an applied vibration with an acceleration amplitude of 0.33m/s^2 at a frequency of 53Hz.
Analysis of Chopper Ripple Reduction by Delayed Sampling
Chopping is widely used to mitigate 1/f noise and offset of amplifiers, e.g., in implantable biomedical devices where very-low-frequency signals are of interest. The main disadvantages of chopping is the degradation of input impedance and the presence of chopping ripples superposing the recorded neural signal. These ripples are especially critical in sampled systems, as back-folding into the baseband should be avoided. Additionally, loop linearity and stability can be compromised by chopping ripples in feedback systems. This article compares ripple reduction strategies from prior art and presents a mathematical analysis of a simple and effective technique by delayed sampling. A description of the signal chain is derived in order to develop a model, which is subsequently used to demonstrate the effectiveness of the presented method. System-level simulations verify the functionality and yield a 30dB ripple reduction at virtually no additional hardware expense.
|16:30-18:35||B5 | Digital Circuits II|
Chair: Franco Maloberti, University of Pavia, Italy
A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section
In this paper, we propose a novel approximate implementation for the Delayed Least Mean Square (DLMS) filter, able to improve the power consumption while preserving the learning capabilities. We exploit the absolute value of the error signal to update the filter coefficients. Indeed, in steady state, the most significant bits of the module of the error are always low, and allow a reduction of the switching activity and of the power consumption in the learning section of the filter. Moreover, we also approximate the FIR section of the filter by using a novel approximate fused multipliers-adder tree, exploiting a partial products cancellation and correction technique. Simulation results show that the convergence properties of the proposed filters are practically unchanged with respect to the original DLMS algorithm. Syntheses in 28 nm technology show a power saving of 53.7% that surpass the state of the art.
An Integrated Multi-Order Digital Control Unit for Maximum Length Sequence Circulant Matrix Generation
In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit’s operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2 MHz clock frequency and has been realized in CMOS 28 nm FD-SOI technology with a total area occupation of 45 µm x 45 µm. From the RTL synthesis, a total power consumption of 8.2 µW is obtained.
Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment
Systems on Chip (SoCs) built around processor(s) must provide more and more computing power while ensuring high reliability. In order to ensure a precise reliability assessment, both hardware architecture and software load should be considered. We focus here on understanding the impact of software characteristics on SoC fault tolerance. The first step was to develop a versatile profiling tool based on a virtual platform adapted to many processors. This analysis flow has been applied on the RISC-V target and Mibench softwares, allowing us to formulate hypotheses on fault tolerance analyses.
Mitigating Cache Contention-Based Attacks by Logical Associativity
Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.
Phase-change memory cells characterization in an analog in-memory computing perspective
Power consumption related to data transfers between processing and memory units has become a critical issue in the recent data-centric outlook of integrated circuits. In the context of In-memory Computing (IMC), where data conveyance is narrowed performing computations directly within the memory unit, Phase-change Memory (PCM) technology has become an attractive candidate due to its intrinsic multilevel storage capability. The test vehicle of this work is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. In this framework, a preliminary characterization of PCM cells has been carried out, aimed at evaluating their performance as enabling devices for analog in-memory computing (AIMC) applications.
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration
Safety is one of the key rules for several application domains like automotive, avionics and the generally called Mission Critical applications. Over the past few years, a plethora of complex systems capable of executing smart applications were introduced in Edge Computing nodes, many of those require the availability of large amounts of data and computational resources, as some advanced AI edge devices rely on many integrated accelerated vector coprocessors that perform ML or DSP applications. On the other hand, safety being a key requirement mandates that the system be fault tolerant. In this paper, we present a comprehensive investigation about the integration of a configurable vector acceleration unit in a fault tolerant RISC-V soft core, introducing a redundant vector coprocessor suitable for all safety critical domains.
A novel fully digital particle detector with high spatial resolution
In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256 × 256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.
|16:30-18:35||C5 | Power Electronics|
Chair: Alberto Gola, Power Integrations, Switzerland
Design of an LLC Resonant DC-DC Converter with MOSFET-Based Active Rectifier
This paper presents an LLC resonant DC-DC converter suitable for low voltage applications. The circuit, designed and simulated in a standard 180-nm BCD process, employs a MOSFET-based active rectifier in order to minimize conduction losses, thus increasing the efficiency at heavy load. The circuit operates with an input voltage of 5 V (±10%), an output voltage of 12 V, and provides to the output a maximum power of 2 W. Transistor level simulation results show an efficiency of 84% at full output power.
A 240 V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm2
This paper presents a fully integrated high-voltage switched-capacitor DC-DC converter in a GaN-on-SOI process. This technology offers high-quality GaN HEMTs with a higher breakdown voltage and lower parasitic capacitances for the same on-resistance as conventional silicon transistors. The presented series-parallel converter integrates the whole converter on a single GaN-die, including the power switches, the gate drivers, and the capacitors. Simulations show an efficiency of 62.6% at a power density of 220 mW/mm2 while converting a 240 V input voltage into an output voltage of 47.5 V. To the author’s knowledge, the proposed converter is the first fully integrated DC-DC converter in GaN. Additionally, it has a 3x higher power density and a higher efficiency compared to previously reported monolithic high-voltage converters.
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control
The open-loop transfer function provides valuable insights into the key dynamic characteristics of DC/DC voltage regulators, such as stability, line and load transient response. Nonetheless, the experimental measurement of the loop gain in a monolithically integrated regulator is not straightforward or not even possible by using standard techniques, especially when complex control strategies are adopted. To overcome this issue, we propose an integrated loop-gain measurement circuit specifically designed for DC/DC converters with time-based control. The measurement circuit includes a transconductor, two delay lines, and a simple logic that can be easily integrated in a small silicon area. Moreover, the circuit can be easily disabled during normal operation to minimize its impact on the regulator performance. The proposed circuit was fabricated in a 180nm CMOS technology, occupying a silicon area of 0.027mm2. Experimental validation was performed by embedding the circuit into a boost converter with time-based control.
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters
Time-based control is a valid alternative to conventional voltage-mode, since it operates with CMOS-level signals while adding no quantization error. This control methodology is especially suitable for voltage regulation in portable applications, where area and power consumption are key parameters. In boost converters powering LED displays, a very fast response to disturbances in the line voltage is required, though the typical right-half-plane (RHP) zero in their control-output transfer function tends to cause large overshoots and long settling times. To solve this issue, we propose a novel feedforward technique, which can be easily combined to the time-based control. The technique is based on adding the band-pass-filtered line voltage to the controller input, to speed up the duty-cycle variation. To assess the effectiveness of this method, theoretical analysis and simulation results are proposed.
Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter
In this work, a design methodology of a step-down (buck) DC-DC converter is presented focusing on the output power stage. The target system is a synchronous buck converter for general purpose applications, which works in a wide range of input and output voltages. The analysis has been focused on the power conversion efficiency that represents one of the major features of this device. Its efficiency is strictly related to the power MOS losses, both conduction and switching ones. The design methodology has been organized into three steps: the first one is the characterization of the power MOS parasites (both resistive and capacitive) with particular attention to temperature and gate driving voltage; in the second step, the power losses are evaluated according to parasitic at different temperature and driving condition of the power MOS; in the last step, the theoretical calculation is verified with the simulation. In particular, the technology used in this work is a 0.16 um Advanced BCD Technology and the simulation environment used is the Cadence Virtuoso suite.
A Fully-Differential Delay-Line Based Control for Resonant Switched-Capacitor Converter
This paper presents a new control method to regulate the output current of a resonant switched-capacitor converter (ReSCC). Starting from a fixed switching frequency operation, the phase-shift required to regulate the average output current is modulated through a fully-differential control scheme composed by a fully-differential OTA, a differential compensation network and two identical voltage-controlled delay lines. The proposed method eliminates any restriction on the minimum achievable phase-shift, is suitable for integration in a scaled technology and for high-frequency operation. Moreover, it allows a seamless control between output current sourcing and sinking capabilities, extending the load current range, and improving the response to load transients. A circuit design has been performed on a 110-nm BCD technology, with 3.7 V to 1.8 V voltage conversion, 60 mA of output current and 10 MHz operation. Simulations demonstrate the effectiveness of the proposed method.
Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters
This paper presents a first mathematical model for estimating the output spectrum spurs of dual-path hybrid (DPH) DC-DC converters and proposes a ΔΣ-modulation control technique to reduce harmonic spikes. The proposed model is hand-calculation friendly and can ensure reasonable accuracy. It features the prediction of the output spectrum spurs that can compromise the noise characteristic of the converters. We also propose a spur reduction method using a 2-2 MASH ΔΣ-modulator to replace the conventional pulse-width modulation control, realizing a 4th order noise shaping function for better noise and limit-cycle spike suppression with relaxed stability issue. Simulation results show that the ΔΣ-modulation controlled DPH converter achieves a spectrum spike reduction of 17.6dB and 15.2 dB in low- and high-frequency conditions, respectively, compared with PWM control.
|16:30-18:35||D5 | Circuits and Systems for Photonic Applications|
Chair: Salvatore Pennisi, University of Catania, Italy
Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology
The design of an integrated 40A pulsed driver for ToF LiDAR in GaN-on-SOI technology is presented. The produced laser current, generated by a resonant circuit, can achieve sub-nanosecond rise time. The design aims to optimally exploit GaN technology, mitigating source bounce effects and compensating the lack of complementary devices, while preserving reliability. The integration process minimizes parasitics via wafer-level-chip-scale packaging (WLCSP), enhancing the performance of the driver.
CMOS driving circuit operating down to 77 K for single-photon emitting diode
A fully-integrated CMOS driving circuit for single-photon emitting diodes in silicon, optimized for space applications, is presented. The electronics comprises two 10-bit DACs in order to precisely set the on and off voltages of the diode based on the measured temperature by an integrated temperature sensor. A large driving voltage range of 0-5 V guarantees the maximum flexibility in the working temperature range from 77 K to 300 K. The chip also contains a pulse generator, capable of driving the diode with short pulses down to 20 ns triggered by an external signal, which is essential in a single-photon light source. The integrated circuit is realized in standard 150-nm CMOS technology, with a chip area of 1.2 mm^2 and a power consumption less than 6mW.
On-chip integrated Schottky photodetectors based on graphene-embedded silicon waveguides
In last years, the introduction of new materials such as graphene has led to advances in the performances of silicon-based photonic devices. Here, we present an innovative type of photodetector based on a graphene/silicon Schottky junction operating at 1.55μm. The device is integrated into a waveguide, where the absorbing layer of graphene is physically embedded between the crystalline silicon and the hydrogenated amorphous silicon so that it is superimposed at the maximum intensity of the propagating mode. We demonstrate the Schottky behaviour of the Gr/c-Si junction, getting a potential barrier of 0.72eV. In a preliminary optical analysis, the PD showed an internal responsivity of 0.15A/W at 1540nm when a reverse bias of -4V is applied to the junction. We believe that this work can pave the way for new solutions in the field of the photonic integrated circuits by exploiting the cheap and mature silicon-microelectronics technologies.
Near-Infrared Graphene/4H-SiC Schottky Photodetectors
Silicon Carbide (SiC), with its superior electronic properties, is recognized as one of the most promising candidates for the new generation of optoelectronic devices. In the present work, a preliminary study about a graphene/4H-SiC Schottky junction photodiode operating in the near-infrared (NIR) spectral range was performed. In particular, we report about the fabrication and the electro-optical characterization of the first - to the best of our knowledge - graphene/4H-SiC-based Schottky near-infrared photodetector. Concerning the electrical characterization, the I-V plot shows a good rectifying behavior, with a series resistance of 64.6 Ω, an ideality factor of 7.30, and a zero-bias Schottky barrier height of 0.498 eV. Ten devices, with the same geometry, were also optically characterized at the wavelength of λ=785 nm, which is far away from the absorption edge of the used wide bandgap semiconductor. The maximum internal responsivity without bias-voltage was evaluated as 0.12 mA/W. Even if the measured responsivity is still limited, we believe that this device can pave the way to investigations on near-infrared Schottky photodetectors based on graphene/4H-SiC junctions, useful for communications at the common fiber optic wavelengths.
Non-invasive light sensor with enhanced sensitivity for photonic integrated circuits
Complex photonic architectures integrated into a single silicon chip require real-time control to keep each device at the desired working point. With this aim, non-invasive optical sensors are an effective solution, allowing to monitor the light inside optical waveguides without penalties in the photonic functionality. Here, the working principle of the CLIPP sensor and its electronic readout are presented and discussed in order to understand how to improve the performance and scale down the size. An improved version of the CLIPP is then presented, featuring a 10-fold improvement in the sensitivity and reaching unprecedented performance for transparent detectors, while also maintaining a small area occupation. Finally, a differential CLIPP readout scheme is discussed, which allows to mitigate the effect of common-mode disturbances.
An Open-Circuit Voltage Pixel in a Standard CMOS Process for Low-Light Visible Imaging
An imaging pixel unit-cell topology leveraging a photodiode in the forward-bias region is proposed for the visible and near-infrared spectral ranges. The open-circuit voltage pixel (VocP) architecture applied to imaging in the visible spectrum allows for improvement in the effective responsivity of the photo detector, leading to significant enhancement in pixel sensitivity across a wide spectral range, while relaxing the requirements on the photodiode, and chosen CMOS process. Theoretical analysis is presented to show the operation, response, and performance benefits of the VocP. The pixel topology has been verified in simulation in the context of a 0.13 μm standard CMOS technology, and the pixel has been embedded in an end-to-end readout system model to show the projected performance compared against a conventional 4T APS.
A Novel Mixed-Signal Silicon Photomultiplier with Analog-Domain Cross-Correlation Computation for LiDAR Applications
Light Detection and Ranging (LiDAR) is a widespread technique for distance measurements used in several applications. In this work, a novel Mixed-Signal Silicon Photomultiplier (msSiPM) with analog-domain cross-correlation computation for LiDAR applications is presented. Cross-correlation technique is commonly implemented at the end of the LiDAR system signal chain to estimate the Time-of-Flight (ToF) and to calculate the measured distance. In this work, an innovative way of performing an approximated cross-correlation inside the detector frontend is presented and simulated. In particular, the typical impulse response of an analog-SiPM (aSiPM) with a specific dead-time is replaced by a custom impulse response by means of a microcell-level Pulse Shaper stage. In this way, is possible to tune the pulse to approximate the time-reversed shape of the laser envelope and to perform an analog cross-correlation. Simulations have been carried out in MATLAB software: by using an msSiPM instead of an aSiPM, an advantage in terms of Signal-to-Noise Ratio (SNR) of 6dB and of Signal-to-Background Ratio (SBR) of about 23dB is obtained.
|Wednesday, June 15th|
|08:45-10:00||A6 | Circuits and Interfaces for Neural Recording|
Chair: Franco Maloberti, University of Pavia, Italy
How to design an input stage for neural recording system in 22 nm FDSOI
The increase of recording channels in modern electrode-based neural recording systems is limited by considerations of power. Emerging CMOS technologies like 22 nm FDSOI promise to open new perspectives in overcoming power constraints due to their particular energy efficiency in digital circuit integration, they however also pose a challenge for the analogue front-end stages of such systems, especially with respect to signal noise. This paper addresses the design of low noise amplifiers (LNA), the most critical component with respect to power and noise, in this technology and application. Moreover, a trade-off between igs-shot noise and flicker noise is described, which leads to the design of the LNA's operational amplifier, minimising noise for a given current. Capacitor types vary in leakage and hence in noise. We therefore simulated and analysed different types and sizes of DC-decoupling capacitors for an estimation of the minimum-area requirement of the LNA. Notably, the described design approaches the minimum input-referred noise possible for a given current and input capacitor in this technology.
Low Power Spike Detector for Brain-Silicon Interface using Differential Amplitude Slope Operator
High-density implantable microelectrode arrays allow to study in-vivo a wide neuron population with the help thousands of integrated electrodes. Such a high electrodes count generates a large amount of data which poses severe challenges in the design of long-term implantable silicon interfaces that rely on a limited power budget and a narrow transmission bandwidth. In such a scenario, reliable spike detectors are needed, as they allow to transmit only the relevant neural information (the neuron action potential) instead of the whole raw recording. Spike detectors based on energy operators provide a good compromise between detection performance and hardware complexity. However, they require a suitable smoothing filter that affects both area occupation and power dissipation. In this paper, we propose a spike detector based on the cascade of two energy operators, without smoothing, and the use of a new simple adaptative threshold calculation. We show that this technique provides good detection metrics compared to previous approaches, for different SNR levels and with several noise models. The proposed system has been synthesized in 28 nm CMOS showing a per-channel area occupation of 0.0021 mm2 with a power consumption of 0.15 µW, comparing favorably with the state of art of brain machine silicon interfaces.
Sub-µW Front-End Low Noise Amplifier for Neural Recording Applications
Multi-channel neural recording systems are more and more required for neuroscience research and to cope with neurological disorders. Such systems are based on brain- implantable integrated devices with stringent requirements on supply voltage, power consumption and area footprint. A very low power, low noise fully differential front-end amplifier for neural signals processing is presented in this paper. The pro- posed amplifier architecture exploits two fully differential OTAs with Arbel topology operating in sub-threshold, and allows AC coupling with a high offset electrode while guaranteeing a very low high-pass cut-off frequency without increasing the equivalent input noise. The neural recording front-end has been designed referring to a 0.13-µm CMOS process. The proposed amplifier operates with a supply voltage as low as 0.3V with a mid-band gain of 40dB and a -3dB bandwidth from 0.1 Hz to 10 kHz. Input referred noise and total power consumption are 11 µVrms and 277nW respectively.
Development of an Analog Front-End for Brain-Computer Interfaces
In the context of the development of an implantable embedded system interfacing brain activity and enabling paralyzed patients to interact with devices that are usable on an everyday basis, we designed a real-time-suitable, low-power hardware architecture with an artifact-suppressing analog front-end, connected to a neural signal processing pipeline. As part of the ultra low-noise analog front-end (four-channel), the common average referencing (CAR) algorithm is implemented to reduce spurious signals from the environment by recording the adjacent electrodes of an invasive microelectrode array (MEA). A Field-Programmable Gate Array (FPGA) is used for data acquisition of extracellular spike activity and data transmission via Ethernet to a host computer for external processing of neural signals. The presented prototype achieves an SNR of 38 dB by applying spike inputs with amplitudes of 100 µV using commercially available components.
|08:45-10:15||B6 | Power and Data Transmission|
Chair: Giovanni Frattini, Analog Devices, Italy
Complementary High-Voltage Compliant High-Current Output Stages for PoDL
This paper presents the design of two complementary high-voltage compliant high-current output stages manufactured in an 0.18 μm high-voltage CMOS technology. The proposed circuits provide a high-voltage compliant monolithic interface for conventional current-steering digital-to-analog converters in the context of Power over Data Lines (PoDL) for Automotive Ethernet. The proposed output stages differ in their function as current sink or current source. Both are composed of improved active-feedback cascode current mirrors with a very large input to output current ratio of 1:50. The current source is the first reported high-voltage compliant current source featuring this topology in a two-stage design. Both circuits offer the widest reported output range for high-voltage compliant current output stages at 500mA. With a passband gain of 34dB, both proposed circuits do also extend the state-of-the-art in terms of the achieved gain-bandwidth product at 544MHz and 656MHz respectively.
A Switched Capacitor Approach for Power Line Communication in Differential Networks
In this paper, a direct modulated Power Line Com- munication (PLC) technique is presented, which realizes the transmitter part by a switched-capacitor (SC) implementation. It is shown that in terms of energy, latency and costs, the presented transmission scheme is advantageous compared to state-of-the- art carrier based solutions. The two variants of the transmitter being analyzed are using an unshielded twisted-pair (UTP) cable to connect the network nodes differentially, while the supply of the nodes are embedded simultaneously. This PLC approach has been verified by discrete component based demonstrator and by a transmitter test chip in 180nm HV-CMOS SOI technology.
StrongArm-Latch-Based Receiver for Supply Line Embedded Communication
A PLC receiver based on a StrongArm Latch with tunable hysteresis is developed to realize a supply line embedded transceiver for automotive application. Modern cars are complex systems with a huge number of distributed Electronic Control Units (ECUs) with even more sensors and actuators included. As automotive systems became more complex, new solutions to drastically reduce the amount of cabling must be developed. A supply embedded communication method does not require a dedicated communication bus, and can be used to decrease weight, cost, and raw materials usage. A key block of the required transceiver is the here proposed receiver that is based on a StrongArm Latch with tunable hysteresis to guarantee performance robustness and circuit sensitivity. A differential buffer and an input divider are used in front of the Latch to provide stable and manageable signal. The full transceiver is developed in a 180nm CMOS SOI technology. Extended simulations in an automotive environment model validate the proposal.
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils
This paper proposes a system to transfer both mW-power and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.
Simultaneous Wireless Power and Data Transmission Through a Single Inductive Link For Multiple Implantable Medical Devices
Inductive power transfer (IPT) is a developing technique for wireless power and data communication systems in the application of implanted medical devices (IMDs). Multiple implants are developed to cover large areas and satisfy the clinical requirements of distributed and long-term biological data acquisition or treatment. In this paper, an analysis of wirelessly-powered implants is proposed to efficiently provide the required power to send and receive data from multiple implants to the external unit. The concept of using different operation frequencies for each implant is also presented, while data transmission employs amplitude and load shift keying (ASK and LSK) for forward and backward telemetry, respectively.
|08:45-10:15||C6 | Synthesis and exploration|
Multi-harvesting smart solution for self-powered wearable objects
Energy harvesting technology provides a promising alternative to batteries usage in low power systems. The integration of these solutions on the same silicon support is a real technological and technical challenge. This paper suggests a multi-harvesting fully-integrated system architecture combining AC and DC sources. Based on a MATLAB/Simulink model, the proposed system allows the calibration of an optimal solution. It is designed and simulated in 40 nm CMOS process, proving that using an AC source as second input, allows to start a harvesting system with very low DC source as main source.
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling
This work presents a study of two analog front-end circuit architectures for heartbeat detection. Both circuits present an amplification block as the first stage, followed by a band-pass filter. In the first, the heartbeat detection is done using an adaptive threshold based on pulse-width, whereas the heartbeat detection in the second is done using a sample and hold to find the maximum and minimum peak of each beating. Both architectures are modeled in Verilog-A and simulated using real-world ECG signals with different characteristics. This study proposes possible fundamental analog circuit blocks suitable for wearable healthcare implementations, and their critical performances, such as noise or bandwidth, are determined from analysis of the behavior simulations. The first architecture can properly detect until an input-referred noise of 21 µV, whereas the second one ensures until 30 µV. The low cutoff frequency can be higher approximately 10 Hz without compromising the signal’s peaks.
Behaivoral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing
In recent years, in-memory computing (IMC) is a promising technique to solve the bottleneck of data movement in edge AI devices. To perform some simple computation in memory, the IMC designs often adopt analog operations, which may incur inevitable computation errors. To recover the accuracy loss, adding some random disturbance in CNN training is a straight-forward approach to make it more tolerant to computation errors. However, random values may be quite different to the real run-time errors caused by non-ideal effects. In this work, we propose a hierarchical simulation framework for the IMC systems to support error-aware CNN training. This framework includes an efficient approach to build accurate IMC behavioral models that reflect real non-ideal effects. By using the behavioral model, an accurate high-level error model can be built efficiently to provide run-time errors for CNN training and error rate verification. As shown in the simulation results, the error-aware CNN training with the proposed models efficiently improves the CNN accuracy in real applications with almost no accuracy loss.
High-level design of a novel PUF based on RTN
PUFs have emerged as an alternative to traditional Non-Volatile Memories in the field of lightweight hardware security. Recently, a novel PUF has been presented that uses the Random Telegraph Noise phenomenon as the underlying source of entropy. While, in general, the nature of that entropy source largely dictates the quality of a PUF, little attention is often paid, however, to how the PUF architecture and its building blocks also impact the PUF quality. This paper addresses the high-level design of the novel PUF to ascertain the extent of that impact and refine the building blocks specifications to minimize it. Using high-level numerical and mixed-signal, high-level electrical simulations, the results demonstrate that it is important to account for non-idealities in the PUF’s building blocks to prevent PUF quality degradation.
An Efficient Hierarchical Approach for Synthesis of Multi-Stage Wide-Band Amplifiers
This paper proposes an efficient approach for hierarchical synthesis of multi-stage wide-band amplifiers. The proposed technique follows a bottom up design scheme. At the bottom level, a multi-objective algorithm (SPEA-2) is employed to obtain the Pareto-optimal front (POF) of a single-stage wide-band amplifier. Then, the obtained Pareto-optimal points (POPs) are combined one by one to constitute the POFs at the higher levels. Here, instead of simulating all possible candidate solutions, we employ an equation-based model including the loading effects of the following stage(s) to estimate the performance at the higher levels. Finally, we extract the final POF from the obtained POPs by using the SPEA-2 selection procedure. Once the POF of a two-stage amplifier is obtained, this circuit is encapsulated as an single amplifier by itself in order to construct the further stages in the hierarchy. Thus, this method can be applied to optimization of multi-stage amplifier circuits regardless of the number of stages. Synthesis results have indicated that a flat optimization approach for a three stage wide-band amplifier requires about 4.5 times the number of iterations compared to the proposed approach for a similar POF, with each iteration requiring a much longer simulation time as well.
|08:45-10:15||D6 | Analysis and verification|
Semi-Symbolic Transient Analysis of Analog Fractional-Order Systems
The concept of algorithmic semi-symbolic transient analysis of analog circuits containing fractional-order elements is described. From the circuit model, the transfer function in symbolic and semi-symbolic form and its w-domain poles are found, the decomposition of the transfer function into partial fractions is performed, and the waveform formula expressed by two-parametric Mittag-Leffler functions and their derivatives are found for each fraction. The formula is then converted into a numerical result. The method is implemented in the SNAP program, and its usefulness is demonstrated on a cascade filter with multiple complex poles.
A Hybrid Model Checking and Theorem Proving based Approach for Fault Tree Analysis
Static fault trees (SFT)s are used for conducting dependability analysis and thus are extensively utilized in various functional safety standards defined by the IEC and ISO for automotive applications. Traditionally, SFTs are manually developed by domain experts through a very cumbersome and error prone process. Once the SFT is available, quantitative fault tree analysis (FTA) is carried out using analytical approaches, e.g., probabilistic model checking and theorem proving. While the former is limited to exponential distributions, the latter can analyze fault trees (FT)s with arbitrary probability distributions. This paper proposes to combine model checking-based automatic FT generation and theorem proving based FTA to ensure a more rigorous and complete approach for FTA. The proposed approach particularly utilizes 1) the xSAP safety assessment platform to automatically generate SFTs from a functionally verified system model and 2) the HOL4 theorem prover to analyze the xSAP-generated SFTs. The usefulness of the approach is illustrated using the case study of an automated vehicle system.
Runtime Monitoring of c-LTL Specifications on FPGAs using HLS
Runtime monitoring is a lightweight verification technique that ensures correct execution of a system based on a correctness specification, e.g. in Linear Temporal Logic (LTL). c-LTL is an extended semantics of LTL that speculates on the property's future satisfaction, by this, warning before potentially violating a correctness specification. Our framework generates high-level synthesizable C++ code implementing runtime monitors for c-LTL properties. We evaluate the resource utilization and performance of the monitors obtained from the framework. Synthesis techniques and our dedicated optimizations cut down the required number of LUTs by up to 93%, allowing an effective implementation of runtime monitors.
Characterization of a Multisource Angle of Arrival Estimation Technique based on Phase Interferometry
Radiolocation made by using space-spectral function based techniques, like MUSIC algorithm, demonstrated to be very efficient but also greedy of computational resources. In this work we present a behavioral characterization of the Multisource I/Q Low-Pass Mixing (M-IQ LPM) algorithm for multiple incoherent sources AoA estimation, taking into account for most of the well-known artifacts-generator phenomena that impact the position estimation. The analysis is performed through simulation investigating also the influence of the number of sources to identify on the overall estimation quality.
Real Number Modeling of a SAR ADC behavior using SystemVerilog
The advances in fabrication technology increase complexity of integrated circuits (ICs) achieving even higher integration. Modern ICs encompass multiple analog, mixed-mode, and digital blocks requiring pre-silicon verification steps for testing functionality efficiently using a unified top simulating environment. Real Number Modeling (RNM) allows a full-system digital simulation in a significantly reduced operation time. A SystemVerilog (SV) behavioral model using RNM for an N-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented using a monotonic capacitive digital-to-analog converter (DAC), and a cascaded output series offset cancellation comparator. The 8-bit version of the proposed model is compared to a transistor-level SPICE model SAR ADC at a standard 180-nm CMOS technology using Spectre Simulator.
|10:45-12:15||A7 | Biomedical Electronics|
Chair: Gianluca Giustolisi, University of Catania, Italy
Acquisition RX Chain for PMUT-Based Highly Integrated Ultrasound Imaging Systems
This paper presents a design solution for a PMUT RX front-end for high performance portable ultrasound medical imaging systems. The PMUT transducer is part of a 1D array working in the 1-4 MHz frequency range. Adequate SNR and low power dissipation are ensured in the RX path thanks to a careful design flow focused onto specific imaging requirements, extracted considering the lumped-parameter equivalent circuit model of the transducer. Programmable gain [25 dB − 35 dB] is implemented to comply with a wide range of input acoustic pressure while distortion parameters are designed in order to provide good imaging qualities. Transistor level design and simulations performed in a BCD-SOI 0.16-µm technology are shown as well.
Analysis of Current-Reuse and Split-Voltage Topology for Biomedical Amplifier Arrays
This paper presents the analysis of two low-power noise-efficient multichannel amplifier topologies, the current-reuse and the split-voltage amplifier, using lateral BJT input transistors. The calculated noise, noise-efficiency factor (NEF), and power consumption is compared with simulation results in a 350nm CMOS technology. The designed current-reuse amplifier has a NEF of 3.19 with an input referred noise floor of 8.3 nV/√Hz and the split-voltage amplifier has a NEF of 2.2 and a noise floor of 5.7 nV/√Hz.
SoC for Retinal Ganglion Cell Stimulation with Integrated Sinusoidal Kilohertz Frequency Waveform Generation
For retinal prostheses strategies to increase the stimulative cell selectivity are required to generate neural responses to electrical stimulation of retinal ganglion cells (RGCs) that match the response of the natural signal pathway. An important part of these strategies is the modulation of stimulus amplitude and frequency in the kilohertz range. The aim of this research is to investigate the electronic challenges and requirements of new electrical stimulation strategies for future retinal implants. This paper presents a 36 channel current controlled stimulator which is able to stimulate retinal tissue with sinusoidal frequencies higher than 1 kHz at amplitudes of up to 200 µA. The power efficiency of the stimulator is 87.3 % at a supply voltage of 1.8 V. One stimulator requires a respective area of 0.0071 mm² by using a 180 nm CMOS technology.
A wearable electronic system for EEG recording
The past decade has been characterized by an impressive surge of wearable electronics devices for biopotential recording applications. Due to its important potential impact, the recording of EEG (electroencephalography) signals recently raised considerable interest within this new paradigm of human-electronics interfacing. Ideally, this application would require minimally-invasive wearable acquisition devices and highly comfortable recording electrodes, two important and complex features that have not been completely resolved. The main problems concerning the implementation of a wearable electronic system for EEG recordings are thus related, on one hand, to the processing/acquisition electronic board and, on the other hand, to the employed acquisition electrodes and their contact with the skin. In particular, the readout electronics for this application should be low-power and possibly easy to integrate in a wearable system, while the electrodes should be as imperceptible as possible, thus allowing comfortable long-term acquisitions. With the intent of providing an efficient solution to both issues, we propose here a low-power and wearable electronic system for EEG monitoring that has been preliminary validated by the means of ultra-conformable epidermal electrodes.
An Automatic Tuning System to Improve Near-Field Powering in Implanted Electronics
Developments in the field of inductive charging have opened the door to the use of devices without a battery or with a wireless rechargeable battery. Although this aspect is significant in the field of wearable devices, it is even more significant in the field of transcutaneous connections for implanted electronics and batteries that can greatly benefit the safety and comfort of the patient. The performance on the ability to transmit and store energy through an inductive channel can, however, be influenced by various environmental and manufacturing factors, with significant variations on the effective values of the LC resonant pair. In this regard, an automatic tuning mechanism based on a SAR algorithm implemented in 180nm CMOS technology is proposed.
|10:45-12:33||B7 | Cryptography and Neural Networks|
Chair: Patrick Haspel, Synopsys, Germany
The DD-Cell: a Double Side Entropic Source exploitable as PUF and TRNG
In this work we demonstrate that the DD-cell, previously proposed by the authors to implement weak PUFs, can behave also as a TRNG, thus allowing the implementation of PUF and TRNG primitives based on the same entropy source. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA device, and both PUF and TRNG functions have been verified through an extensive measurement campaign involving PVT variations. Measurements results have shown that the entropy of a DD-cell can reach a value higher than 0.99 without requiring any post-processing.
Programmable delay lines on different LUT implementations for CRO-PUF
In this paper we analyze the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA due to differences in detailed routing at LUT level. The different PUF configurations for a given set of ring oscillators are generated using programmable delay lines on the cells realizing the inverters, while only one LUT input is used for the propagation of the oscillations along the ring. This architecture is suitable for implementation in FPGA, so the experiments have been conducted on Xilinx's Zynq SoC.
An analysis of ring oscillator PUF behaviour depending on the ring oscillator locations
In this paper, an analysis regarding the influence of the chosen locations of the ring oscillators in the performance of a ring oscillator Physically Unclonable Function has been carried out. For this purpose, five different strategies to select a small set of locations out of a big set of locations to construct a PUF have been proposed and compared. The analysis reflects that, depending on the chosen selection strategy, the quality of the PUF can be greatly affected, especially in terms of uniqueness.
Leaky Integrate-and-Fire Neuron with a Refractory Period Mechanism for Invariant Spikes
Spiking neural networks (SNNs) are a widespread research topic, as they are a promising solution for efficient and low-energy signal processing. The advantage in energy consumption of SNN algorithms pre-developed in software is obtained by their transfer to neural application-specific integrated circuits (ASICs). The neurons and synapses that are used on algorithm level have to be mapped by special circuits on the hardware level. One of the most widely used neuron models due to its low computational complexity and high biological inspiration is the leaky integrate-and-fire (LIF) neuron. In this paper, a modification of an energy-efficient LIF neuron is presented with a novel method to use a refractory period (RP) to generate invariant output spikes. By modifying the RP mechanism, the controllability and stability of entire SNN systems on the circuit level can be significantly improved. Due to the low energy of 1.4 pJ / spike and the invariance of these, it becomes easier to predict the total energy consumption of a large-scale SNN. The concept is verified in measurement by fabricating the circuit in a 130nm BiCMOS process.
A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron
Simulation is a particularly significant component of discovery and hypothesizing in neuroscience. Given the typical complexity of the mathematical models involved in neuromorphic modelling, neuromorphic hardware for acceleration is an interesting topic of research. Thus, a novel, high-accuracy digital implementation of the Fitzhugh-Nagumo neuron is realized on FPGA. The proposed system offers substantial hardware resource savings and a higher clock frequency compared to previously proposed implementations. For these reasons, it is an excellent candidate for use in hardware acceleration of neuroscientific simulation. The implemented hardware achieves a normalized RMSE of 0.2451 at a maximum operation frequency of 367.78MHz.
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators
Reconfigurable computing has become very popular in recent years. Among all available architectures, Coarse-Grained Reconfigurable Arrays are the most prominent ones. They permit to efficiently accelerate several classes of data-intensive algorithms without giving up architecture versatility, and their use in machine learning applications is becoming increasingly widespread. In particular, the typical workload of Convolutional Neural Networks fits very well on this kind of architecture. Unfortunately, their use in the most advanced Graph Neural Networks is not well investigated. Graph Neural Network algorithms apply to all kinds of use cases that are characterized by non-euclidean data, such as computer vision, natural language processing, traffic forecasting, chemistry, and recommendation systems. In this work, we analyse the most relevant Coarse-Grained Reconfigurable Array devices and Graph Neural Network models. Our contribution includes a comparison between the hardware architectures and their use for the inference of Graph Neural Network models. We highlight their limitations and discuss possible directions that the development of these architectures could take.
|10:45-12:15||C7 | Design methodologies|
Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/ºC Temperature Coefficient
This paper describes a radiation-hardened bandgap voltage reference (BGR) for space applications. The BGR has a second-order curvature compensation and can deliver a stable output voltage and current for N-type and P-type loads through internal resistors or, optionally, through an external precision resistor. The circuit includes three 8-bit trimming resistive ladders for post-fabrication calibration of the temperature compensation slope, output voltage, and output current value. The circuit is designed for reliable performance in space application, considering process, voltage, and temperature variations and the impact of single-event transients and total ionizing dose. The BGR was designed in a 180 nm silicon-on-insulator CMOS technology, using radiation-hardened devices to provide a 1.25 V reference voltage and a 20 µA current reference, and occupies a 920×430 µm2 area. After trimming, the nominal post-layout simulation over the temperature range of -40 to 125°C shows the BGR achieving a 2.7 ppm/°C temperature coefficient, 6.13 ppm/°C in the worst case.
Mixed-Variable Bayesian Optimization for Analog Circuit Sizing using Variational Autoencoders
Bayesian Optimization (BO) has recently gained popularity within the context of automatic sizing of analog and Radio-Frequency (RF) Integrated Circuits (ICs). However, its reliance on Gaussian Process models, which operate only on continuous-valued spaces, reduces its applicability in realworld scenarios, where multiple discrete-valued variables often exist. In this paper, we propose an approach to mitigate this issue by using a Deep Learning scheme to transform devices parametrizations to continuous ones, where classic BO can be applied. Specifically, a composite architecture that consists of a Convolutional Variational Autoencoder (VAE) and a dense Neural Network is built to define a continuous representation of integrated inductors in a TSMC 90nm process. By optimizing using these representations, we overcome the limitation of discretevalued variables. Experimental results on a Low Noise Amplifier highlight the efficiency of the proposed approach.
Design Methodology for an Adjustable-Range CMOS Smart Temperature Sensor
In this work, a design methodology for adjusting the full-scale range of CMOS temperature sensors utilizing ΣΔ modulators for biomedical applications is proposed, aiming to relax design requirements. A sample sensor system is presented as a case study to obtain 30◦C dynamic range by utilizing different unit MIM capacitor branches with a first-order ΣΔ modulator topology. Simulation results of the designed temperature sensor show 0.03◦C resolution by using 0.18mm2 silicon area in a 0.18μm CMOS technology. By utilizing the proposed design methodology based on mathematical extrapolation, it is demonstrated that the obligation of the minimum second-order ΣΔ ADC based temperature sensor design is eliminated by more efficient use of the full-scale range, achieving a cost-effective design in terms of power and design complexity.
Current-Mode Electronically-Tunable Sinusoidal Oscillator Based on a Shadow Bandpass Filter
The design of a current-mode frequency and amplitude-controlled sinusoidal oscillator, is presented. The oscillator is based on a second order Gm-C bandpass filter made up of low-voltage current mirror cells. The frequency response of the filter can be modified by means of its biasing current. Besides, an automatic control circuit that ensures oscillation and leads to the desired amplitude of the output signal, has been included. The proposal has been designed and implemented in 180 nm CMOS technology to operate with a supply voltage of 1.8 V, resulting in a compact solution very appropriate for operation in low-voltage environments. The simulated results show high speed, with a maximum bandwidth of 2.75 MHz, and linear response, with a THD of around −40 dB for an output amplitude of 5 μA.
Verification of an Active Time Constant Tuning Technique for Continuous-Time Delta-Sigma Modulators
In this work we present a technique to compensate the effects of R-C / gm-C time-constant (TC) errors due to process variation in continuous-time delta-sigma modulators. Local TC error compensation factors are shifted around in the modulator loop to positions where they can be implemented efficiently with finely tunable circuit structures, such as current-steering digital-to-analog converters (DAC). We apply our technique to a third-order, single-bit, low-pass continuous-time delta-sigma modulator in cascaded integrator feedback structure, implemented in a 0.35-μm CMOS process. A tuning scheme for the reference currents of the feedback DACs is derived as a function of the individual TC errors and verified by circuit simulations. We confirm the tuning technique experimentally on the fabricated circuit over a TC parameter variation range of ±20 %. Stable modulator operation is achieved for all parameter sets. The measured performances satisfy the expectations from our theoretical calculations and circuit-level simulations.
|10:45-12:15||D7 | Device modeling and analysis|
Responsivity Comparison of Different Photodiode Structures
Silicon-based photodiodes with different topologies are designed and simulated using the Sentaurus Technology Computer-Aided Design (TCAD) tool. These topologies comprise i) a conventional device with a single n-well, ii-iii) two versions of a branched (interdigitated) structure with a regular well, iv-v) a ring-like well structure with two different contact configurations, and finally vi) a structure that has a well in the center of the device. Designed devices are simulated with incident light within various wavelengths from 0.6 um to 0.7 um. The effect of the reflection coefficients of anode and cathode contacts is also investigated. The ring-like structure is the most effective in producing the highest cathode current for a given input optical power. Doping type effects are inquired as well.
Level 3 Based SPICE Model for Low-Voltage Pentacene Thin Film Transistors
A modeling technique is presented for organic thin film transistors (OTFTs) using Level 3 MOSFET model with additional four model parameters in the LTspice platform. First, the mobility model equation is simplified. Next, the evaluated drain current of the Level 3 model is manipulated proportionally to the recently proposed OTFT mobility model. On the other hand, the model performance is enhanced in the subthreshold regime adding off-state current. This behavioral model is built by using one PMOS transistor and two behavioral current sources. Then, the Level 3 DC model parameters are obtained fitting the model equations to the low-voltage pentacene-based OTFT data using previously studied metaheuristics-based parameter extraction approach. Finally, the behavioral model based on Level 3 model is simulated in LTspice while the gate and drain voltages are both ranging from 0 to –3 V. It is validated within this range comparing the experimental and modeled characteristic current-voltage curves. This model can be more convenient for very large OTFT-based digital circuit simulations.
An Improved Model for Metal Oxide-Based Memristors and Application in Memory Crossbars
Owing to their valuable properties, memristors are applicable in neural networks, memory crossbars, analog and digital programmable devices and others, and their design require simplified memristor models with a good precision. In this paper, a simple, accurate, highly nonlinear and fast operating metal oxide-based memristor model is proposed. Due to the use of a sine hyperbolic dependence between the time derivative of the state variable and voltage, the suggested model has a high precision and correctly represents the nonlinear dopant drift. Its equivalent LTSPICE library model includes activation thresholds and a differentiable sigmoid function, which prevents convergence problems. The model is applied and analyzed in a simple memory matrix. The model’s operation is in a good agreement with the main fingerprints of the memristors. Its correct functioning and applicability in complex electronic schemes are established.
Teaching the MOSFET: A Circuit Designer’s View
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are the most common components within integrated circuits. That is why they are commonly taught in the courses of study for electrical engineers. Despite hundreds of papers and books on MOSFETs the intuitive explanation of its behavior rises questions of the students especially for the explanation of saturation behavior. Why is the current limited by the charge carriers that are in the semiconductor substrate and form the inversion layer? There is an almost infinite reservoir available from the battery and the terminals, isn't there? Why do the sets of characteristic curves not continue to follow the parabola instead of remaining constant from the peak point (transition from linear to saturation region)? The paper shows both the consistent and causal derivation of the Level 1 MOSFET behavior from a few equations and the illustrative explanations for students to understand this behavior. Finally, an outlook is given on today’s MOSFET models and the difficulties in interpreting especially their AC parameters.
2T-3R-4V-3C Subcircuit Model for SiC Gate Turn-off Thyristors with High Convergence
In this article, we build on our previous research and propose a compact subcircuit model (2T-3R-4V-3C model) for silicon carbide (SiC) gate turn-off thyristors (GTOs), in which conduction, blocking, and switching performance are all characterized. The overall model is composed of two submodels in parallel, each submodel contains two bipolar junction transistors (BJTs), three resistors, four DC voltage sources and three capacitors, the delay between two submodels and parasitic effects are considered. The capacitances are used to reflect the conductivity modulation effect in the switching process, and the voltage sources represent the difference in forward voltage drop between the Si junction and the SiC junction. The parameter extraction method is discussed, and compared with the previous work, the new model avoids the large-range adjustment of parameters in the order of magnitude, so the convergence is greatly improved. The measured data of a self-fabricated 4H-SiC GTO is used to validate the model, and the results show a higher degree of accuracy than previous work.
|14:30-15:30||T2 | Tutorial II|
Introduction to Co-Packaged Opto-Electronics Design
|15:30-16:30||I4 | Industrial Talks IV|
Integrated sensorless motor controller for cooling system in EV (Allegro)
IPCEI on microelectronics at FBK: a project fostering the development of innovative Smart Sensors (FBK)
MEMS Microphones new requirements and challenges (TDK)